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This is an interrupt-controller implemented in an FPGA, to multiplex interrupts generated from other IPs. The FPGA usually uses a GPIO as a parent interrupt controller to notify that one of the multiplexed interrupts has triggered. Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: kernel@savoirfairelinux.com Link: http://lkml.kernel.org/r/1450728683-31416-1-git-send-email-damien.riegel@savoirfairelinux.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
17 lines
696 B
Plaintext
17 lines
696 B
Plaintext
TS-4800 FPGA interrupt controller
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TS-4800 FPGA has an internal interrupt controller. When one of the
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interrupts is triggered, the SoC is notified, usually using a GPIO as
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parent interrupt source.
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Required properties:
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- compatible: should be "technologic,ts4800-irqc"
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- interrupt-controller: identifies the node as an interrupt controller
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- reg: physical base address of the controller and length of memory mapped
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region
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- interrupt-parent: phandle to the parent interrupt controller this one is
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cascaded from
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- interrupts: specifies the interrupt line in the interrupt-parent controller
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