mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 05:27:00 +07:00
a4240d3af6
DRA72-EVM now has an upgrade to Rev C with SR2.0 silicon. As part of this change, a few updates were factored in that were software incompatible with previous board in few areas: - We now use DP83867 ethernet phy instead of older DP838865 which fails in certain use cases. - Two Ethernet ports now instead of the single one in rev B. - polarities changed for certain pcf gpios - Due to SoC phy current requirements, VDDA supplies are split between ldo3 and ldo2 (ldo2 was previously unused). NOTE: DSS (VDDA_VIDEO) is still supplied by ldo5, HDMI is now supplied by LDO2 instead of using LDO3. NOTE: It does not make much sense to spin off a new board compatible flag since there is no real benefit for the same. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
834 lines
22 KiB
Plaintext
834 lines
22 KiB
Plaintext
/*
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* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra72x.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/ti-dra7-atl.h>
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/ {
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
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aliases {
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display0 = &hdmi0;
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};
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evm_3v3: fixedregulator-evm_3v3 {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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aic_dvdd: fixedregulator-aic_dvdd {
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/* TPS77018DBVT */
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compatible = "regulator-fixed";
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regulator-name = "aic_dvdd";
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vin-supply = <&evm_3v3>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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evm_3v3_sd: fixedregulator-sd {
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compatible = "regulator-fixed";
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regulator-name = "evm_3v3_sd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
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};
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extcon_usb1: extcon_usb1 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
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};
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extcon_usb2: extcon_usb2 {
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compatible = "linux,extcon-usb-gpio";
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id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
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};
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hdmi0: connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "a";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&tpd12s015_out>;
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};
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};
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};
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tpd12s015: encoder {
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compatible = "ti,tpd12s015";
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pinctrl-names = "default";
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pinctrl-0 = <&tpd12s015_pins>;
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gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
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<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
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<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpd12s015_in: endpoint {
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remote-endpoint = <&hdmi_out>;
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};
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};
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port@1 {
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reg = <1>;
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tpd12s015_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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sound0: sound0 {
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compatible = "simple-audio-card";
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simple-audio-card,name = "DRA7xx-EVM";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line Out",
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"Microphone", "Mic Jack",
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"Line", "Line In";
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simple-audio-card,routing =
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"MIC3L", "Mic Jack",
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"MIC3R", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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simple-audio-card,format = "dsp_b";
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simple-audio-card,bitclock-master = <&sound0_master>;
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simple-audio-card,frame-master = <&sound0_master>;
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simple-audio-card,bitclock-inversion;
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sound0_master: simple-audio-card,cpu {
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sound-dai = <&mcasp3>;
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system-clock-frequency = <5644800>;
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};
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simple-audio-card,codec {
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sound-dai = <&tlv320aic3106>;
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clocks = <&atl_clkin2_ck>;
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};
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};
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};
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&dra7_pmx_core {
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
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DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
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>;
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};
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i2c5_pins: pinmux_i2c5_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
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DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
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>;
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};
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i2c5_pins: pinmux_i2c5_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
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DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
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>;
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};
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nand_default: nand_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
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DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
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DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
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DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
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DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
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DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
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DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
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DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
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DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
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DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
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DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
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DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
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DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
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DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
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DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
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DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
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DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
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DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
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DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
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DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
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DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
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DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
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>;
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};
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usb1_pins: pinmux_usb1_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
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>;
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};
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usb2_pins: pinmux_usb2_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
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>;
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};
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tps65917_pins_default: tps65917_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
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>;
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};
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mmc1_pins_default: mmc1_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
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DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
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DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
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DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
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DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
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DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
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DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
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>;
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};
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mmc2_pins_default: mmc2_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
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DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
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DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
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DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
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DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
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DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
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DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
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DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
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DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
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DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
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>;
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};
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dcan1_pins_default: dcan1_pins_default {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
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DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
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>;
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};
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dcan1_pins_sleep: dcan1_pins_sleep {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
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DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
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>;
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};
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qspi1_pins: pinmux_qspi1_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
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DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
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DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
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DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
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DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
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DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
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DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
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>;
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};
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hdmi_pins: pinmux_hdmi_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
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DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
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>;
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};
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tpd12s015_pins: pinmux_tpd12s015_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
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>;
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};
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atl_pins: pinmux_atl_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
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DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
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>;
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};
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mcasp3_pins: pinmux_mcasp3_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
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DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
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DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
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DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
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>;
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};
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mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
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pinctrl-single,pins = <
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DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
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DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
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DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
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DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
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>;
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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tps65917: tps65917@58 {
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compatible = "ti,tps65917";
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reg = <0x58>;
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pinctrl-names = "default";
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pinctrl-0 = <&tps65917_pins_default>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,system-power-controller;
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tps65917_pmic {
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compatible = "ti,tps65917-pmic";
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tps65917_regulators: regulators {
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smps1_reg: smps1 {
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/* VDD_MPU */
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regulator-name = "smps1";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps2_reg: smps2 {
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/* VDD_CORE */
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regulator-name = "smps2";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1060000>;
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regulator-boot-on;
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regulator-always-on;
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};
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smps3_reg: smps3 {
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/* VDD_GPU IVA DSPEVE */
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regulator-name = "smps3";
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-boot-on;
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regulator-always-on;
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};
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smps4_reg: smps4 {
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/* VDDS1V8 */
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regulator-name = "smps4";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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smps5_reg: smps5 {
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/* VDD_DDR */
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regulator-name = "smps5";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: ldo1 {
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/* LDO1_OUT --> SDIO */
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regulator-name = "ldo1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-allow-bypass;
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};
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ldo3_reg: ldo3 {
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/* VDDA_1V8_PHY */
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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|
|
ldo5_reg: ldo5 {
|
|
/* VDDA_1V8_PLL */
|
|
regulator-name = "ldo5";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
ldo4_reg: ldo4 {
|
|
/* VDDA_3V_USB: VDDA_USBHS33 */
|
|
regulator-name = "ldo4";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
tps65917_power_button {
|
|
compatible = "ti,palmas-pwrbutton";
|
|
interrupt-parent = <&tps65917>;
|
|
interrupts = <1 IRQ_TYPE_NONE>;
|
|
wakeup-source;
|
|
ti,palmas-long-press-seconds = <6>;
|
|
};
|
|
};
|
|
|
|
pcf_gpio_21: gpio@21 {
|
|
compatible = "nxp,pcf8575";
|
|
reg = <0x21>;
|
|
lines-initial-states = <0x1408>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
tlv320aic3106: tlv320aic3106@19 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "ti,tlv320aic3106";
|
|
reg = <0x19>;
|
|
adc-settle-ms = <40>;
|
|
ai3x-micbias-vg = <1>; /* 2.0V */
|
|
status = "okay";
|
|
|
|
/* Regulators */
|
|
AVDD-supply = <&evm_3v3>;
|
|
IOVDD-supply = <&evm_3v3>;
|
|
DRVDD-supply = <&evm_3v3>;
|
|
DVDD-supply = <&aic_dvdd>;
|
|
};
|
|
};
|
|
|
|
&i2c5 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_pins>;
|
|
clock-frequency = <400000>;
|
|
|
|
pcf_hdmi: pcf8575@26 {
|
|
compatible = "nxp,pcf8575";
|
|
reg = <0x26>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
/*
|
|
* initial state is used here to keep the mdio interface
|
|
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
|
|
* VIN2_S0 driven high otherwise Ethernet stops working
|
|
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
|
|
*/
|
|
lines-initial-states = <0x0f2b>;
|
|
|
|
p1 {
|
|
/* vin6_sel_s0: high: VIN6, low: audio */
|
|
gpio-hog;
|
|
gpios = <1 GPIO_ACTIVE_HIGH>;
|
|
output-low;
|
|
line-name = "vin6_sel_s0";
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&dra7_pmx_core 0x3e0>;
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nand_default>;
|
|
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
|
nand@0,0 {
|
|
/* To use NAND, DIP switch SW5 must be set like so:
|
|
* SW5.1 (NAND_SELn) = ON (LOW)
|
|
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
|
*/
|
|
compatible = "ti,omap2-nand";
|
|
reg = <0 0 4>; /* device IO registers */
|
|
interrupt-parent = <&gpmc>;
|
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
|
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
|
|
ti,nand-ecc-opt = "bch8";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <16>;
|
|
gpmc,device-width = <2>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <80>;
|
|
gpmc,cs-wr-off-ns = <80>;
|
|
gpmc,adv-on-ns = <0>;
|
|
gpmc,adv-rd-off-ns = <60>;
|
|
gpmc,adv-wr-off-ns = <60>;
|
|
gpmc,we-on-ns = <10>;
|
|
gpmc,we-off-ns = <50>;
|
|
gpmc,oe-on-ns = <4>;
|
|
gpmc,oe-off-ns = <40>;
|
|
gpmc,access-ns = <40>;
|
|
gpmc,wr-access-ns = <80>;
|
|
gpmc,rd-cycle-ns = <80>;
|
|
gpmc,wr-cycle-ns = <80>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x000020000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00020000 0x00020000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00040000 0x00020000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x00060000 0x00020000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x000c0000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb2_phy1 {
|
|
phy-supply = <&ldo4_reg>;
|
|
};
|
|
|
|
&usb2_phy2 {
|
|
phy-supply = <&ldo4_reg>;
|
|
};
|
|
|
|
&omap_dwc3_1 {
|
|
extcon = <&extcon_usb1>;
|
|
};
|
|
|
|
&omap_dwc3_2 {
|
|
extcon = <&extcon_usb2>;
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "peripheral";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb1_pins>;
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&usb2_pins>;
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins_default>;
|
|
vmmc-supply = <&evm_3v3_sd>;
|
|
vmmc_aux-supply = <&ldo1_reg>;
|
|
bus-width = <4>;
|
|
/*
|
|
* SDCD signal is not being used here - using the fact that GPIO mode
|
|
* is a viable alternative
|
|
*/
|
|
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
|
|
max-frequency = <192000000>;
|
|
};
|
|
|
|
&mmc2 {
|
|
/* SW5-3 in ON position */
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_pins_default>;
|
|
|
|
vmmc-supply = <&evm_3v3>;
|
|
bus-width = <8>;
|
|
ti,non-removable;
|
|
max-frequency = <192000000>;
|
|
};
|
|
|
|
&dra7_pmx_core {
|
|
cpsw_default: cpsw_default {
|
|
pinctrl-single,pins = <
|
|
/* Slave 2 */
|
|
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
|
|
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
|
|
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
|
|
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
|
|
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
|
|
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
|
|
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
|
|
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
|
|
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
|
|
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
|
|
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
|
|
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
|
|
>;
|
|
|
|
};
|
|
|
|
cpsw_sleep: cpsw_sleep {
|
|
pinctrl-single,pins = <
|
|
/* Slave 2 */
|
|
DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_default: davinci_mdio_default {
|
|
pinctrl-single,pins = <
|
|
/* MDIO */
|
|
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
|
|
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
|
>;
|
|
};
|
|
|
|
davinci_mdio_sleep: davinci_mdio_sleep {
|
|
pinctrl-single,pins = <
|
|
DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
|
|
DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
|
|
>;
|
|
};
|
|
};
|
|
|
|
&mac {
|
|
status = "okay";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
};
|
|
|
|
&dcan1 {
|
|
status = "ok";
|
|
pinctrl-names = "default", "sleep", "active";
|
|
pinctrl-0 = <&dcan1_pins_sleep>;
|
|
pinctrl-1 = <&dcan1_pins_sleep>;
|
|
pinctrl-2 = <&dcan1_pins_default>;
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&qspi1_pins>;
|
|
|
|
spi-max-frequency = <48000000>;
|
|
m25p80@0 {
|
|
compatible = "s25fl256s1";
|
|
spi-max-frequency = <48000000>;
|
|
reg = <0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
spi-cpol;
|
|
spi-cpha;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* MTD partition table.
|
|
* The ROM checks the first four physical blocks
|
|
* for a valid file to boot and the flash here is
|
|
* 64KiB block size.
|
|
*/
|
|
partition@0 {
|
|
label = "QSPI.SPL";
|
|
reg = <0x00000000 0x000010000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.SPL.backup1";
|
|
reg = <0x00010000 0x00010000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.SPL.backup2";
|
|
reg = <0x00020000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.SPL.backup3";
|
|
reg = <0x00030000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.u-boot";
|
|
reg = <0x00040000 0x00100000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00140000 0x00080000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x001c0000 0x00010000>;
|
|
};
|
|
partition@7 {
|
|
label = "QSPI.u-boot-env.backup1";
|
|
reg = <0x001d0000 0x0010000>;
|
|
};
|
|
partition@8 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x001e0000 0x0800000>;
|
|
};
|
|
partition@9 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x009e0000 0x01620000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dss {
|
|
status = "ok";
|
|
|
|
vdda_video-supply = <&ldo5_reg>;
|
|
};
|
|
|
|
&hdmi {
|
|
status = "ok";
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_pins>;
|
|
|
|
port {
|
|
hdmi_out: endpoint {
|
|
remote-endpoint = <&tpd12s015_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&atl {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&atl_pins>;
|
|
|
|
assigned-clocks = <&abe_dpll_sys_clk_mux>,
|
|
<&atl_gfclk_mux>,
|
|
<&dpll_abe_ck>,
|
|
<&dpll_abe_m2x2_ck>,
|
|
<&atl_clkin2_ck>;
|
|
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
|
|
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
|
|
|
|
status = "okay";
|
|
|
|
atl2 {
|
|
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
|
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
|
};
|
|
};
|
|
|
|
&mcasp3 {
|
|
#sound-dai-cells = <0>;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&mcasp3_pins>;
|
|
pinctrl-1 = <&mcasp3_sleep_pins>;
|
|
|
|
assigned-clocks = <&mcasp3_ahclkx_mux>;
|
|
assigned-clock-parents = <&atl_clkin2_ck>;
|
|
|
|
status = "okay";
|
|
|
|
op-mode = <0>; /* MCASP_IIS_MODE */
|
|
tdm-slots = <2>;
|
|
/* 4 serializer */
|
|
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
|
1 2 0 0
|
|
>;
|
|
tx-num-evt = <32>;
|
|
rx-num-evt = <32>;
|
|
};
|
|
|
|
&mailbox5 {
|
|
status = "okay";
|
|
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
|
status = "okay";
|
|
};
|
|
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&mailbox6 {
|
|
status = "okay";
|
|
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
|
status = "okay";
|
|
};
|
|
};
|