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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dbaf381ffb
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
180 lines
5.7 KiB
C
180 lines
5.7 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
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#define __DT_BINDINGS_CLOCK_IMX6SL_H
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#define IMX6SL_CLK_DUMMY 0
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#define IMX6SL_CLK_CKIL 1
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#define IMX6SL_CLK_OSC 2
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#define IMX6SL_CLK_PLL1_SYS 3
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#define IMX6SL_CLK_PLL2_BUS 4
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#define IMX6SL_CLK_PLL3_USB_OTG 5
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#define IMX6SL_CLK_PLL4_AUDIO 6
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#define IMX6SL_CLK_PLL5_VIDEO 7
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#define IMX6SL_CLK_PLL6_ENET 8
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#define IMX6SL_CLK_PLL7_USB_HOST 9
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#define IMX6SL_CLK_USBPHY1 10
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#define IMX6SL_CLK_USBPHY2 11
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#define IMX6SL_CLK_USBPHY1_GATE 12
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#define IMX6SL_CLK_USBPHY2_GATE 13
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#define IMX6SL_CLK_PLL4_POST_DIV 14
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#define IMX6SL_CLK_PLL5_POST_DIV 15
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#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
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#define IMX6SL_CLK_ENET_REF 17
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#define IMX6SL_CLK_PLL2_PFD0 18
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#define IMX6SL_CLK_PLL2_PFD1 19
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#define IMX6SL_CLK_PLL2_PFD2 20
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#define IMX6SL_CLK_PLL3_PFD0 21
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#define IMX6SL_CLK_PLL3_PFD1 22
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#define IMX6SL_CLK_PLL3_PFD2 23
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#define IMX6SL_CLK_PLL3_PFD3 24
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#define IMX6SL_CLK_PLL2_198M 25
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#define IMX6SL_CLK_PLL3_120M 26
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#define IMX6SL_CLK_PLL3_80M 27
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#define IMX6SL_CLK_PLL3_60M 28
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#define IMX6SL_CLK_STEP 29
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#define IMX6SL_CLK_PLL1_SW 30
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#define IMX6SL_CLK_OCRAM_ALT_SEL 31
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#define IMX6SL_CLK_OCRAM_SEL 32
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#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
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#define IMX6SL_CLK_PRE_PERIPH_SEL 34
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#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
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#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
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#define IMX6SL_CLK_CSI_SEL 37
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#define IMX6SL_CLK_LCDIF_AXI_SEL 38
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#define IMX6SL_CLK_USDHC1_SEL 39
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#define IMX6SL_CLK_USDHC2_SEL 40
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#define IMX6SL_CLK_USDHC3_SEL 41
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#define IMX6SL_CLK_USDHC4_SEL 42
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#define IMX6SL_CLK_SSI1_SEL 43
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#define IMX6SL_CLK_SSI2_SEL 44
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#define IMX6SL_CLK_SSI3_SEL 45
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#define IMX6SL_CLK_PERCLK_SEL 46
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#define IMX6SL_CLK_PXP_AXI_SEL 47
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#define IMX6SL_CLK_EPDC_AXI_SEL 48
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#define IMX6SL_CLK_GPU2D_OVG_SEL 49
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#define IMX6SL_CLK_GPU2D_SEL 50
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#define IMX6SL_CLK_LCDIF_PIX_SEL 51
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#define IMX6SL_CLK_EPDC_PIX_SEL 52
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#define IMX6SL_CLK_SPDIF0_SEL 53
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#define IMX6SL_CLK_SPDIF1_SEL 54
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#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
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#define IMX6SL_CLK_ECSPI_SEL 56
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#define IMX6SL_CLK_UART_SEL 57
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#define IMX6SL_CLK_PERIPH 58
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#define IMX6SL_CLK_PERIPH2 59
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#define IMX6SL_CLK_OCRAM_PODF 60
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#define IMX6SL_CLK_PERIPH_CLK2_PODF 61
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#define IMX6SL_CLK_PERIPH2_CLK2_PODF 62
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#define IMX6SL_CLK_IPG 63
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#define IMX6SL_CLK_CSI_PODF 64
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#define IMX6SL_CLK_LCDIF_AXI_PODF 65
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#define IMX6SL_CLK_USDHC1_PODF 66
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#define IMX6SL_CLK_USDHC2_PODF 67
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#define IMX6SL_CLK_USDHC3_PODF 68
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#define IMX6SL_CLK_USDHC4_PODF 69
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#define IMX6SL_CLK_SSI1_PRED 70
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#define IMX6SL_CLK_SSI1_PODF 71
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#define IMX6SL_CLK_SSI2_PRED 72
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#define IMX6SL_CLK_SSI2_PODF 73
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#define IMX6SL_CLK_SSI3_PRED 74
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#define IMX6SL_CLK_SSI3_PODF 75
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#define IMX6SL_CLK_PERCLK 76
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#define IMX6SL_CLK_PXP_AXI_PODF 77
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#define IMX6SL_CLK_EPDC_AXI_PODF 78
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#define IMX6SL_CLK_GPU2D_OVG_PODF 79
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#define IMX6SL_CLK_GPU2D_PODF 80
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#define IMX6SL_CLK_LCDIF_PIX_PRED 81
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#define IMX6SL_CLK_EPDC_PIX_PRED 82
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#define IMX6SL_CLK_LCDIF_PIX_PODF 83
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#define IMX6SL_CLK_EPDC_PIX_PODF 84
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#define IMX6SL_CLK_SPDIF0_PRED 85
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#define IMX6SL_CLK_SPDIF0_PODF 86
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#define IMX6SL_CLK_SPDIF1_PRED 87
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#define IMX6SL_CLK_SPDIF1_PODF 88
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#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
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#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
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#define IMX6SL_CLK_ECSPI_ROOT 91
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#define IMX6SL_CLK_UART_ROOT 92
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#define IMX6SL_CLK_AHB 93
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#define IMX6SL_CLK_MMDC_ROOT 94
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#define IMX6SL_CLK_ARM 95
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#define IMX6SL_CLK_ECSPI1 96
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#define IMX6SL_CLK_ECSPI2 97
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#define IMX6SL_CLK_ECSPI3 98
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#define IMX6SL_CLK_ECSPI4 99
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#define IMX6SL_CLK_EPIT1 100
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#define IMX6SL_CLK_EPIT2 101
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#define IMX6SL_CLK_EXTERN_AUDIO 102
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#define IMX6SL_CLK_GPT 103
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#define IMX6SL_CLK_GPT_SERIAL 104
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#define IMX6SL_CLK_GPU2D_OVG 105
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#define IMX6SL_CLK_I2C1 106
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#define IMX6SL_CLK_I2C2 107
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#define IMX6SL_CLK_I2C3 108
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#define IMX6SL_CLK_OCOTP 109
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#define IMX6SL_CLK_CSI 110
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#define IMX6SL_CLK_PXP_AXI 111
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#define IMX6SL_CLK_EPDC_AXI 112
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#define IMX6SL_CLK_LCDIF_AXI 113
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#define IMX6SL_CLK_LCDIF_PIX 114
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#define IMX6SL_CLK_EPDC_PIX 115
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#define IMX6SL_CLK_OCRAM 116
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#define IMX6SL_CLK_PWM1 117
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#define IMX6SL_CLK_PWM2 118
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#define IMX6SL_CLK_PWM3 119
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#define IMX6SL_CLK_PWM4 120
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#define IMX6SL_CLK_SDMA 121
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#define IMX6SL_CLK_SPDIF 122
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#define IMX6SL_CLK_SSI1 123
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#define IMX6SL_CLK_SSI2 124
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#define IMX6SL_CLK_SSI3 125
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#define IMX6SL_CLK_UART 126
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#define IMX6SL_CLK_UART_SERIAL 127
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#define IMX6SL_CLK_USBOH3 128
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#define IMX6SL_CLK_USDHC1 129
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#define IMX6SL_CLK_USDHC2 130
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#define IMX6SL_CLK_USDHC3 131
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#define IMX6SL_CLK_USDHC4 132
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#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
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#define IMX6SL_CLK_SPBA 134
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#define IMX6SL_CLK_ENET 135
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#define IMX6SL_CLK_LVDS1_SEL 136
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#define IMX6SL_CLK_LVDS1_OUT 137
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#define IMX6SL_CLK_LVDS1_IN 138
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#define IMX6SL_CLK_ANACLK1 139
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#define IMX6SL_PLL1_BYPASS_SRC 140
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#define IMX6SL_PLL2_BYPASS_SRC 141
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#define IMX6SL_PLL3_BYPASS_SRC 142
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#define IMX6SL_PLL4_BYPASS_SRC 143
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#define IMX6SL_PLL5_BYPASS_SRC 144
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#define IMX6SL_PLL6_BYPASS_SRC 145
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#define IMX6SL_PLL7_BYPASS_SRC 146
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#define IMX6SL_CLK_PLL1 147
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#define IMX6SL_CLK_PLL2 148
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#define IMX6SL_CLK_PLL3 149
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#define IMX6SL_CLK_PLL4 150
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#define IMX6SL_CLK_PLL5 151
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#define IMX6SL_CLK_PLL6 152
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#define IMX6SL_CLK_PLL7 153
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#define IMX6SL_PLL1_BYPASS 154
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#define IMX6SL_PLL2_BYPASS 155
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#define IMX6SL_PLL3_BYPASS 156
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#define IMX6SL_PLL4_BYPASS 157
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#define IMX6SL_PLL5_BYPASS 158
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#define IMX6SL_PLL6_BYPASS 159
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#define IMX6SL_PLL7_BYPASS 160
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#define IMX6SL_CLK_SSI1_IPG 161
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#define IMX6SL_CLK_SSI2_IPG 162
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#define IMX6SL_CLK_SSI3_IPG 163
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#define IMX6SL_CLK_END 164
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#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
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