mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 10:37:45 +07:00
abb90a24ea
The nds32 architecture will use physical memory when interrupt or exception comes and it will use the setting of NTC0-4. The original implementation didn't consider the DRAM start address may start from 1GB, 2GB or 3GB to cause this issue. It will write the data to DRAM if it is running in physical address however kernel will read the data with virtaul address through data cache. In this case, the data of DRAM is latest. This fix will set the correct cacheability to let kernel write/read the latest data in cache instead of DRAM. Signed-off-by: Greentime Hu <greentime@andestech.com>
207 lines
5.5 KiB
ArmAsm
207 lines
5.5 KiB
ArmAsm
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/sizes.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define OF_DT_MAGIC 0xd00dfeed
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#else
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#define OF_DT_MAGIC 0xedfe0dd0
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, TEXTADDR - 0x4000
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/*
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* Kernel startup entry point.
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*/
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.section ".head.text", "ax"
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.type _stext, %function
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ENTRY(_stext)
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setgie.d ! Disable interrupt
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isb
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/*
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* Disable I/D-cache and enable it at a proper time
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*/
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mfsr $r0, $mr8
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li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN)
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and $r0, $r0, $r1
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mtsr $r0, $mr8
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/*
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* Process device tree blob
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*/
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andi $r0,$r2,#0x3
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li $r10, 0
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bne $r0, $r10, _nodtb
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lwi $r0, [$r2]
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li $r1, OF_DT_MAGIC
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bne $r0, $r1, _nodtb
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move $r10, $r2
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_nodtb:
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/*
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* Create a temporary mapping area for booting, before start_kernel
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*/
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sethi $r4, hi20(swapper_pg_dir)
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li $p0, (PAGE_OFFSET - PHYS_OFFSET)
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sub $r4, $r4, $p0
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tlbop FlushAll ! invalidate TLB\n"
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isb
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mtsr $r4, $L1_PPTB ! load page table pointer\n"
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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#define MMU_CTL_NTCC MMU_CTL_CACHEABLE_NON
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#else
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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#define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WT
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#else
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#define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WB
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#endif
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#endif
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/* set NTC cacheability, mutliple page size in use */
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mfsr $r3, $MMU_CTL
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#if CONFIG_MEMORY_START >= 0xc0000000
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ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC3)
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#elif CONFIG_MEMORY_START >= 0x80000000
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ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC2)
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#elif CONFIG_MEMORY_START >= 0x40000000
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ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC1)
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#else
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ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC0)
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#endif
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#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
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ori $r3, $r3, #(MMU_CTL_mskMPZIU)
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#else
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ori $r3, $r3, #(MMU_CTL_mskMPZIU|MMU_CTL_D8KB)
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#endif
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#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS
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li $r0, #MMU_CTL_UNA
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or $r3, $r3, $r0
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#endif
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mtsr $r3, $MMU_CTL
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isb
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/* set page size and size of kernel image */
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mfsr $r0, $MMU_CFG
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srli $r3, $r0, MMU_CFG_offfEPSZ
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zeb $r3, $r3
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bnez $r3, _extra_page_size_support
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#ifdef CONFIG_ANDES_PAGE_SIZE_4KB
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li $r5, #SZ_4K ! Use 4KB page size
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#else
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li $r5, #SZ_8K ! Use 8KB page size
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li $r3, #1
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#endif
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mtsr $r3, $TLB_MISC
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b _image_size_check
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_extra_page_size_support: ! Use epzs pages size
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clz $r6, $r3
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subri $r2, $r6, #31
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li $r3, #1
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sll $r3, $r3, $r2
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/* MMU_CFG.EPSZ value -> meaning */
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mul $r5, $r3, $r3
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slli $r5, $r5, #14
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/* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */
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addi $r3, $r2, #0x2
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mtsr $r3, $TLB_MISC
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_image_size_check:
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/* calculate the image maximum size accepted by TLB config */
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andi $r6, $r0, MMU_CFG_mskTBW
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andi $r0, $r0, MMU_CFG_mskTBS
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srli $r6, $r6, MMU_CFG_offTBW
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srli $r0, $r0, MMU_CFG_offTBS
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/*
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* we just map the kernel to the maximum way - 1 of tlb
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* reserver one way for UART VA mapping
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* it will cause page fault if UART mapping cover the kernel mapping
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*
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* direct mapping is not supported now.
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*/
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li $r2, 't'
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beqz $r6, __error ! MMU_CFG.TBW = 0 is direct mappin
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addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning
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sll $r0, $r6, $r0 ! entries = k-way * n-set
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mul $r6, $r0, $r5 ! max size = entries * page size
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/* check kernel image size */
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la $r3, (_end - PAGE_OFFSET)
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li $r2, 's'
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bgt $r3, $r6, __error
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li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
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li $r3, PAGE_OFFSET
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add $r6, $r6, $r3
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_tlb:
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mtsr $r3, $TLB_VPN
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dsb
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tlbop $r2, RWR
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isb
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add $r3, $r3, $r5
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add $r2, $r2, $r5
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bgt $r6, $r3, _tlb
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mfsr $r3, $TLB_MISC ! setup access page size
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li $r2, #~0xf
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and $r3, $r3, $r2
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#ifdef CONFIG_ANDES_PAGE_SIZE_8KB
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ori $r3, $r3, #0x1
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#endif
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mtsr $r3, $TLB_MISC
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mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
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ori $r0, $r0, #MISC_init
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mtsr $r0, $MISC_CTL
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mfsr $p1, $PSW
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li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE
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and $p1, $p1, $r15
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ori $p1, $p1, #PSW_init
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mtsr $p1, $IPSW ! when iret, it will automatically enable MMU
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la $lp, __mmap_switched
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mtsr $lp, $IPC
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iret
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nop
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.type __switch_data, %object
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__switch_data:
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.long __bss_start ! $r6
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.long _end ! $r7
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.long __atags_pointer ! $atag_pointer
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.long init_task ! $r9, move to $r25
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.long init_thread_union + THREAD_SIZE ! $sp
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/*
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* The following fragment of code is executed with the MMU on in MMU mode,
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* and uses absolute addresses; this is not position independent.
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*/
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.align
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.type __mmap_switched, %function
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__mmap_switched:
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la $r3, __switch_data
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lmw.bim $r6, [$r3], $r9, #0b0001
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move $r25, $r9
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move $fp, #0 ! Clear BSS (and zero $fp)
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beq $r7, $r6, _RRT
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1: swi.bi $fp, [$r6], #4
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bne $r7, $r6, 1b
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swi $r10, [$r8]
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_RRT:
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b start_kernel
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__error:
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b __error
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