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Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470) USB PHY is similar to the R-Car Gen2 family, but has the below feature compared to other RZ/G1 and R-Car Gen2/3 SoCs It has a shared pll reset for usbphy0/usbphy1 and this register reside in usbphy0 block. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
112 lines
3.6 KiB
Plaintext
112 lines
3.6 KiB
Plaintext
* Renesas R-Car generation 2 USB PHY
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This file provides information on what the device node for the R-Car generation
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2 USB PHY contains.
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Required properties:
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- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
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"renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
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"renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
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"renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
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"renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
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"renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
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"renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
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"renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or
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RZ/G1 compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: offset and length of the register block.
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- #address-cells: number of address cells for the USB channel subnodes, must
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be <1>.
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- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
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- clocks: clock phandle and specifier pair.
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- clock-names: string, clock input name, must be "usbhs".
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The USB PHY device tree node should have the subnodes corresponding to the USB
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channels. These subnodes must contain the following properties:
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- reg: the USB controller selector; see the table below for the values.
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- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
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The phandle's argument in the PHY specifier is the USB controller selector for
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the USB channel other than r8a77470 SoC; see the selector meanings below:
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+-----------+---------------+---------------+
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|\ Selector | | |
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+ --------- + 0 | 1 |
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| Channel \| | |
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+-----------+---------------+---------------+
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| 0 | PCI EHCI/OHCI | HS-USB |
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| 2 | PCI EHCI/OHCI | xHCI |
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+-----------+---------------+---------------+
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For r8a77470 SoC;see the selector meaning below:
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+-----------+---------------+---------------+
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|\ Selector | | |
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+ --------- + 0 | 1 |
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| Channel \| | |
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+-----------+---------------+---------------+
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| 0 | EHCI/OHCI | HS-USB |
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+-----------+---------------+---------------+
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Example (Lager board):
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usb-phy@e6590100 {
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compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy";
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reg = <0 0xe6590100 0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cpg CPG_MOD 704>;
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clock-names = "usbhs";
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 704>;
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usb0: usb-channel@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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usb2: usb-channel@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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};
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Example (iWave RZ/G1C sbc):
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usbphy0: usb-phy0@e6590100 {
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compatible = "renesas,usb-phy-r8a77470",
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"renesas,rcar-gen2-usb-phy";
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reg = <0 0xe6590100 0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cpg CPG_MOD 704>;
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clock-names = "usbhs";
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 704>;
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usb0: usb-channel@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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};
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usbphy1: usb-phy@e6598100 {
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compatible = "renesas,usb-phy-r8a77470",
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"renesas,rcar-gen2-usb-phy";
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reg = <0 0xe6598100 0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cpg CPG_MOD 706>;
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clock-names = "usbhs";
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power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
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resets = <&cpg 706>;
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usb1: usb-channel@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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};
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