mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 08:37:53 +07:00
3e1aa7cb59
By the nature of the TEST operation, it is often possible to test
a narrower part of the operand:
"testl $3, mem" -> "testb $3, mem",
"testq $3, %rcx" -> "testb $3, %cl"
This results in shorter instructions, because the TEST instruction
has no sign-entending byte-immediate forms unlike other ALU ops.
Note that this change does not create any LCP (Length-Changing Prefix)
stalls, which happen when adding a 0x66 prefix, which happens when
16-bit immediates are used, which changes such TEST instructions:
[test_opcode] [modrm] [imm32]
to:
[0x66] [test_opcode] [modrm] [imm16]
where [imm16] has a *different length* now: 2 bytes instead of 4.
This confuses the decoder and slows down execution.
REX prefixes were carefully designed to almost never hit this case:
adding REX prefix does not change instruction length except MOVABS
and MOV [addr],RAX instruction.
This patch does not add instructions which would use a 0x66 prefix,
code changes in assembly are:
-48 f7 07 01 00 00 00 testq $0x1,(%rdi)
+f6 07 01 testb $0x1,(%rdi)
-48 f7 c1 01 00 00 00 test $0x1,%rcx
+f6 c1 01 test $0x1,%cl
-48 f7 c1 02 00 00 00 test $0x2,%rcx
+f6 c1 02 test $0x2,%cl
-41 f7 c2 01 00 00 00 test $0x1,%r10d
+41 f6 c2 01 test $0x1,%r10b
-48 f7 c1 04 00 00 00 test $0x4,%rcx
+f6 c1 04 test $0x4,%cl
-48 f7 c1 08 00 00 00 test $0x8,%rcx
+f6 c1 08 test $0x8,%cl
Linus further notes:
"There are no stalls from using 8-bit instruction forms.
Now, changing from 64-bit or 32-bit 'test' instructions to 8-bit ones
*could* cause problems if it ends up having forwarding issues, so that
instead of just forwarding the result, you end up having to wait for
it to be stable in the L1 cache (or possibly the register file). The
forwarding from the store buffer is simplest and most reliable if the
read is done at the exact same address and the exact same size as the
write that gets forwarded.
But that's true only if:
(a) the write was very recent and is still in the write queue. I'm
not sure that's the case here anyway.
(b) on at least most Intel microarchitectures, you have to test a
different byte than the lowest one (so forwarding a 64-bit write
to a 8-bit read ends up working fine, as long as the 8-bit read
is of the low 8 bits of the written data).
A very similar issue *might* show up for registers too, not just
memory writes, if you use 'testb' with a high-byte register (where
instead of forwarding the value from the original producer it needs to
go through the register file and then shifted). But it's mainly a
problem for store buffers.
But afaik, the way Denys changed the test instructions, neither of the
above issues should be true.
The real problem for store buffer forwarding tends to be "write 8
bits, read 32 bits". That can be really surprisingly expensive,
because the read ends up having to wait until the write has hit the
cacheline, and we might talk tens of cycles of latency here. But
"write 32 bits, read the low 8 bits" *should* be fast on pretty much
all x86 chips, afaik."
Signed-off-by: Denys Vlasenko <dvlasenk@redhat.com>
Acked-by: Andy Lutomirski <luto@amacapital.net>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Will Drewry <wad@chromium.org>
Link: http://lkml.kernel.org/r/1425675332-31576-1-git-send-email-dvlasenk@redhat.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
552 lines
14 KiB
ArmAsm
552 lines
14 KiB
ArmAsm
/*
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* linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
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*
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* Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
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* Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
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* Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
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* Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
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* Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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#include <asm/segment.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/msr.h>
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#include <asm/cache.h>
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#include <asm/processor-flags.h>
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#include <asm/percpu.h>
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#include <asm/nops.h>
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#ifdef CONFIG_PARAVIRT
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#include <asm/asm-offsets.h>
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#include <asm/paravirt.h>
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#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
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#else
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#define GET_CR2_INTO(reg) movq %cr2, reg
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#define INTERRUPT_RETURN iretq
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#endif
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/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
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* because we need identity-mapped pages.
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*
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*/
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#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
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L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
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L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
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L4_START_KERNEL = pgd_index(__START_KERNEL_map)
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L3_START_KERNEL = pud_index(__START_KERNEL_map)
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.text
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__HEAD
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.code64
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.globl startup_64
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startup_64:
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
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* and someone has loaded an identity mapped page table
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* for us. These identity mapped page tables map all of the
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* kernel pages and possibly all of memory.
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*
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* %rsi holds a physical pointer to real_mode_data.
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*
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* We come here either directly from a 64bit bootloader, or from
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* arch/x86/boot/compressed/head_64.S.
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*
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* We only come here initially at boot nothing else comes here.
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*
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* Since we may be loaded at an address different from what we were
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* compiled to run at we first fixup the physical addresses in our page
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* tables and then reload them.
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*/
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/*
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* Compute the delta between the address I am compiled to run at and the
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* address I am actually running at.
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*/
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leaq _text(%rip), %rbp
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subq $_text - __START_KERNEL_map, %rbp
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/* Is the address not 2M aligned? */
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movq %rbp, %rax
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andl $~PMD_PAGE_MASK, %eax
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testl %eax, %eax
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jnz bad_address
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/*
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* Is the address too large?
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*/
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leaq _text(%rip), %rax
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shrq $MAX_PHYSMEM_BITS, %rax
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jnz bad_address
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/*
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* Fixup the physical addresses in the page table
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*/
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addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
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addq %rbp, level3_kernel_pgt + (510*8)(%rip)
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addq %rbp, level3_kernel_pgt + (511*8)(%rip)
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addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
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/*
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* Set up the identity mapping for the switchover. These
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* entries should *NOT* have the global bit set! This also
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* creates a bunch of nonsense entries but that is fine --
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* it avoids problems around wraparound.
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*/
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leaq _text(%rip), %rdi
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leaq early_level4_pgt(%rip), %rbx
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movq %rdi, %rax
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shrq $PGDIR_SHIFT, %rax
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leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
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movq %rdx, 0(%rbx,%rax,8)
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movq %rdx, 8(%rbx,%rax,8)
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addq $4096, %rdx
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movq %rdi, %rax
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shrq $PUD_SHIFT, %rax
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andl $(PTRS_PER_PUD-1), %eax
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movq %rdx, 4096(%rbx,%rax,8)
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incl %eax
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andl $(PTRS_PER_PUD-1), %eax
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movq %rdx, 4096(%rbx,%rax,8)
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addq $8192, %rbx
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movq %rdi, %rax
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shrq $PMD_SHIFT, %rdi
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addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
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leaq (_end - 1)(%rip), %rcx
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shrq $PMD_SHIFT, %rcx
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subq %rdi, %rcx
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incl %ecx
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1:
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andq $(PTRS_PER_PMD - 1), %rdi
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movq %rax, (%rbx,%rdi,8)
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incq %rdi
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addq $PMD_SIZE, %rax
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decl %ecx
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jnz 1b
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/*
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* Fixup the kernel text+data virtual addresses. Note that
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* we might write invalid pmds, when the kernel is relocated
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* cleanup_highmap() fixes this up along with the mappings
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* beyond _end.
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*/
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leaq level2_kernel_pgt(%rip), %rdi
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leaq 4096(%rdi), %r8
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/* See if it is a valid page table entry */
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1: testb $1, 0(%rdi)
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jz 2f
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addq %rbp, 0(%rdi)
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/* Go to the next page */
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2: addq $8, %rdi
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cmp %r8, %rdi
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jne 1b
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/* Fixup phys_base */
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addq %rbp, phys_base(%rip)
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movq $(early_level4_pgt - __START_KERNEL_map), %rax
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jmp 1f
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ENTRY(secondary_startup_64)
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/*
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* At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
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* and someone has loaded a mapped page table.
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*
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* %rsi holds a physical pointer to real_mode_data.
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*
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* We come here either from startup_64 (using physical addresses)
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* or from trampoline.S (using virtual addresses).
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*
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* Using virtual addresses from trampoline.S removes the need
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* to have any identity mapped pages in the kernel page table
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* after the boot processor executes this code.
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*/
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movq $(init_level4_pgt - __START_KERNEL_map), %rax
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1:
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/* Enable PAE mode and PGE */
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movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
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movq %rcx, %cr4
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/* Setup early boot stage 4 level pagetables. */
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addq phys_base(%rip), %rax
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movq %rax, %cr3
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/* Ensure I am executing from virtual addresses */
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movq $1f, %rax
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jmp *%rax
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1:
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/* Check if nx is implemented */
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movl $0x80000001, %eax
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cpuid
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movl %edx,%edi
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/* Setup EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_SCE, %eax /* Enable System Call */
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btl $20,%edi /* No Execute supported? */
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jnc 1f
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btsl $_EFER_NX, %eax
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btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
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1: wrmsr /* Make changes effective */
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/* Setup cr0 */
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#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
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X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
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X86_CR0_PG)
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movl $CR0_STATE, %eax
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/* Make changes effective */
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movq %rax, %cr0
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/* Setup a boot time stack */
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movq stack_start(%rip), %rsp
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/* zero EFLAGS after setting rsp */
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pushq $0
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popfq
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/*
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* We must switch to a new descriptor in kernel space for the GDT
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* because soon the kernel won't have access anymore to the userspace
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* addresses where we're currently running on. We have to do that here
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* because in 32bit we couldn't load a 64bit linear address.
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*/
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lgdt early_gdt_descr(%rip)
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/* set up data segments */
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xorl %eax,%eax
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movl %eax,%ds
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movl %eax,%ss
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movl %eax,%es
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/*
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* We don't really need to load %fs or %gs, but load them anyway
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* to kill any stale realmode selectors. This allows execution
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* under VT hardware.
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*/
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movl %eax,%fs
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movl %eax,%gs
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/* Set up %gs.
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*
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* The base of %gs always points to the bottom of the irqstack
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* union. If the stack protector canary is enabled, it is
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* located at %gs:40. Note that, on SMP, the boot cpu uses
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* init data section till per cpu areas are set up.
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*/
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movl $MSR_GS_BASE,%ecx
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movl initial_gs(%rip),%eax
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movl initial_gs+4(%rip),%edx
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wrmsr
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/* rsi is pointer to real mode structure with interesting info.
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pass it to C */
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movq %rsi, %rdi
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/* Finally jump to run C code and to be on real kernel address
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* Since we are running on identity-mapped space we have to jump
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* to the full 64bit address, this is only possible as indirect
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* jump. In addition we need to ensure %cs is set so we make this
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* a far return.
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*
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* Note: do not change to far jump indirect with 64bit offset.
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*
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* AMD does not support far jump indirect with 64bit offset.
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* AMD64 Architecture Programmer's Manual, Volume 3: states only
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* JMP FAR mem16:16 FF /5 Far jump indirect,
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* with the target specified by a far pointer in memory.
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* JMP FAR mem16:32 FF /5 Far jump indirect,
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* with the target specified by a far pointer in memory.
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*
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* Intel64 does support 64bit offset.
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* Software Developer Manual Vol 2: states:
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* FF /5 JMP m16:16 Jump far, absolute indirect,
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* address given in m16:16
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* FF /5 JMP m16:32 Jump far, absolute indirect,
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* address given in m16:32.
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* REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
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* address given in m16:64.
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*/
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movq initial_code(%rip),%rax
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pushq $0 # fake return address to stop unwinder
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pushq $__KERNEL_CS # set correct cs
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pushq %rax # target address in negative space
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lretq
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#ifdef CONFIG_HOTPLUG_CPU
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/*
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* Boot CPU0 entry point. It's called from play_dead(). Everything has been set
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* up already except stack. We just set up stack here. Then call
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* start_secondary().
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*/
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ENTRY(start_cpu0)
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movq stack_start(%rip),%rsp
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movq initial_code(%rip),%rax
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pushq $0 # fake return address to stop unwinder
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pushq $__KERNEL_CS # set correct cs
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pushq %rax # target address in negative space
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lretq
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ENDPROC(start_cpu0)
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#endif
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/* SMP bootup changes these two */
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__REFDATA
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.balign 8
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GLOBAL(initial_code)
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.quad x86_64_start_kernel
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GLOBAL(initial_gs)
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.quad INIT_PER_CPU_VAR(irq_stack_union)
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GLOBAL(stack_start)
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.quad init_thread_union+THREAD_SIZE-8
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.word 0
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__FINITDATA
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bad_address:
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jmp bad_address
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__INIT
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.globl early_idt_handlers
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early_idt_handlers:
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# 104(%rsp) %rflags
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# 96(%rsp) %cs
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# 88(%rsp) %rip
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# 80(%rsp) error code
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i = 0
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.rept NUM_EXCEPTION_VECTORS
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.if (EXCEPTION_ERRCODE_MASK >> i) & 1
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ASM_NOP2
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.else
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pushq $0 # Dummy error code, to make stack frame uniform
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.endif
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pushq $i # 72(%rsp) Vector number
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jmp early_idt_handler
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i = i + 1
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.endr
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/* This is global to keep gas from relaxing the jumps */
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ENTRY(early_idt_handler)
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cld
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cmpl $2,(%rsp) # X86_TRAP_NMI
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je is_nmi # Ignore NMI
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cmpl $2,early_recursion_flag(%rip)
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jz 1f
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incl early_recursion_flag(%rip)
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pushq %rax # 64(%rsp)
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pushq %rcx # 56(%rsp)
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pushq %rdx # 48(%rsp)
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pushq %rsi # 40(%rsp)
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pushq %rdi # 32(%rsp)
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pushq %r8 # 24(%rsp)
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pushq %r9 # 16(%rsp)
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pushq %r10 # 8(%rsp)
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pushq %r11 # 0(%rsp)
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cmpl $__KERNEL_CS,96(%rsp)
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jne 11f
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cmpl $14,72(%rsp) # Page fault?
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jnz 10f
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GET_CR2_INTO(%rdi) # can clobber any volatile register if pv
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call early_make_pgtable
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andl %eax,%eax
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jz 20f # All good
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10:
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leaq 88(%rsp),%rdi # Pointer to %rip
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call early_fixup_exception
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andl %eax,%eax
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jnz 20f # Found an exception entry
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11:
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#ifdef CONFIG_EARLY_PRINTK
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GET_CR2_INTO(%r9) # can clobber any volatile register if pv
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movl 80(%rsp),%r8d # error code
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movl 72(%rsp),%esi # vector number
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movl 96(%rsp),%edx # %cs
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movq 88(%rsp),%rcx # %rip
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xorl %eax,%eax
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leaq early_idt_msg(%rip),%rdi
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call early_printk
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cmpl $2,early_recursion_flag(%rip)
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jz 1f
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call dump_stack
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#ifdef CONFIG_KALLSYMS
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leaq early_idt_ripmsg(%rip),%rdi
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movq 40(%rsp),%rsi # %rip again
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call __print_symbol
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#endif
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#endif /* EARLY_PRINTK */
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1: hlt
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jmp 1b
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20: # Exception table entry found or page table generated
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popq %r11
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popq %r10
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popq %r9
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popq %r8
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popq %rdi
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popq %rsi
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popq %rdx
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popq %rcx
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popq %rax
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decl early_recursion_flag(%rip)
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is_nmi:
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addq $16,%rsp # drop vector number and error code
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INTERRUPT_RETURN
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ENDPROC(early_idt_handler)
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__INITDATA
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.balign 4
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early_recursion_flag:
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.long 0
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#ifdef CONFIG_EARLY_PRINTK
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early_idt_msg:
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.asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
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early_idt_ripmsg:
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.asciz "RIP %s\n"
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#endif /* CONFIG_EARLY_PRINTK */
|
|
|
|
#define NEXT_PAGE(name) \
|
|
.balign PAGE_SIZE; \
|
|
GLOBAL(name)
|
|
|
|
/* Automate the creation of 1 to 1 mapping pmd entries */
|
|
#define PMDS(START, PERM, COUNT) \
|
|
i = 0 ; \
|
|
.rept (COUNT) ; \
|
|
.quad (START) + (i << PMD_SHIFT) + (PERM) ; \
|
|
i = i + 1 ; \
|
|
.endr
|
|
|
|
__INITDATA
|
|
NEXT_PAGE(early_level4_pgt)
|
|
.fill 511,8,0
|
|
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
|
|
|
|
NEXT_PAGE(early_dynamic_pgts)
|
|
.fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
|
|
|
|
.data
|
|
|
|
#ifndef CONFIG_XEN
|
|
NEXT_PAGE(init_level4_pgt)
|
|
.fill 512,8,0
|
|
#else
|
|
NEXT_PAGE(init_level4_pgt)
|
|
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
|
|
.org init_level4_pgt + L4_PAGE_OFFSET*8, 0
|
|
.quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
|
|
.org init_level4_pgt + L4_START_KERNEL*8, 0
|
|
/* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
|
|
.quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
|
|
|
|
NEXT_PAGE(level3_ident_pgt)
|
|
.quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
|
|
.fill 511, 8, 0
|
|
NEXT_PAGE(level2_ident_pgt)
|
|
/* Since I easily can, map the first 1G.
|
|
* Don't set NX because code runs from these pages.
|
|
*/
|
|
PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
|
|
#endif
|
|
|
|
NEXT_PAGE(level3_kernel_pgt)
|
|
.fill L3_START_KERNEL,8,0
|
|
/* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
|
|
.quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
|
|
.quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
|
|
|
|
NEXT_PAGE(level2_kernel_pgt)
|
|
/*
|
|
* 512 MB kernel mapping. We spend a full page on this pagetable
|
|
* anyway.
|
|
*
|
|
* The kernel code+data+bss must not be bigger than that.
|
|
*
|
|
* (NOTE: at +512MB starts the module area, see MODULES_VADDR.
|
|
* If you want to increase this then increase MODULES_VADDR
|
|
* too.)
|
|
*/
|
|
PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
|
|
KERNEL_IMAGE_SIZE/PMD_SIZE)
|
|
|
|
NEXT_PAGE(level2_fixmap_pgt)
|
|
.fill 506,8,0
|
|
.quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
|
|
/* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
|
|
.fill 5,8,0
|
|
|
|
NEXT_PAGE(level1_fixmap_pgt)
|
|
.fill 512,8,0
|
|
|
|
#undef PMDS
|
|
|
|
.data
|
|
.align 16
|
|
.globl early_gdt_descr
|
|
early_gdt_descr:
|
|
.word GDT_ENTRIES*8-1
|
|
early_gdt_descr_base:
|
|
.quad INIT_PER_CPU_VAR(gdt_page)
|
|
|
|
ENTRY(phys_base)
|
|
/* This must match the first entry in level2_kernel_pgt */
|
|
.quad 0x0000000000000000
|
|
|
|
#ifdef CONFIG_KASAN
|
|
#define FILL(VAL, COUNT) \
|
|
.rept (COUNT) ; \
|
|
.quad (VAL) ; \
|
|
.endr
|
|
|
|
NEXT_PAGE(kasan_zero_pte)
|
|
FILL(kasan_zero_page - __START_KERNEL_map + _KERNPG_TABLE, 512)
|
|
NEXT_PAGE(kasan_zero_pmd)
|
|
FILL(kasan_zero_pte - __START_KERNEL_map + _KERNPG_TABLE, 512)
|
|
NEXT_PAGE(kasan_zero_pud)
|
|
FILL(kasan_zero_pmd - __START_KERNEL_map + _KERNPG_TABLE, 512)
|
|
|
|
#undef FILL
|
|
#endif
|
|
|
|
|
|
#include "../../x86/xen/xen-head.S"
|
|
|
|
__PAGE_ALIGNED_BSS
|
|
NEXT_PAGE(empty_zero_page)
|
|
.skip PAGE_SIZE
|
|
|
|
#ifdef CONFIG_KASAN
|
|
/*
|
|
* This page used as early shadow. We don't use empty_zero_page
|
|
* at early stages, stack instrumentation could write some garbage
|
|
* to this page.
|
|
* Latter we reuse it as zero shadow for large ranges of memory
|
|
* that allowed to access, but not instrumented by kasan
|
|
* (vmalloc/vmemmap ...).
|
|
*/
|
|
NEXT_PAGE(kasan_zero_page)
|
|
.skip PAGE_SIZE
|
|
#endif
|