Andrew Bresticker f521ac8b39 clk: exynos5250: register APLL rate table ... Register the APLL rate table so that we can set the APLL rate from the cpufreq driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>		2014-01-08 18:01:49 +01:00
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clk-exynos4.c	clk: samsung: exynos4: Correct SRC_MFC register	2013-12-30 17:53:18 +01:00
clk-exynos5250.c	clk: exynos5250: register APLL rate table	2014-01-08 18:01:49 +01:00
clk-exynos5420.c	clk: exynos5420: fix cpll clock register offsets	2013-12-04 10:46:45 -08:00
clk-exynos5440.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk-exynos-audss.c	clk: exynos: File scope reg_save array should depend on PM_SLEEP	2013-12-30 18:01:09 +01:00
clk-pll.c	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-pll.h	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-s3c64xx.c	clk: s3c64xx: Fix incorrect placement of __initdata	2013-08-27 18:36:20 -07:00
clk.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk.h	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
Makefile	ARM: S3C64XX: Migrate clock handling to Common Clock Framework	2013-09-17 06:47:36 +09:00