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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f50b153b19
To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> |
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| .. | ||
| align.c | ||
| asm-offsets.c | ||
| bitops.c | ||
| cpu_setup_6xx.S | ||
| cpu_setup_power4.S | ||
| cputable.c | ||
| dma-mapping.c | ||
| entry.S | ||
| find_name.c | ||
| head_4xx.S | ||
| head_8xx.S | ||
| head_44x.S | ||
| head_booke.h | ||
| head_fsl_booke.S | ||
| head.S | ||
| idle_6xx.S | ||
| idle_power4.S | ||
| idle.c | ||
| irq.c | ||
| l2cr.S | ||
| Makefile | ||
| misc.S | ||
| module.c | ||
| pci.c | ||
| perfmon_fsl_booke.c | ||
| perfmon.c | ||
| ppc_htab.c | ||
| ppc_ksyms.c | ||
| ppc-stub.c | ||
| process.c | ||
| ptrace.c | ||
| semaphore.c | ||
| setup.c | ||
| signal.c | ||
| smp-tbsync.c | ||
| smp.c | ||
| softemu8xx.c | ||
| swsusp.S | ||
| syscalls.c | ||
| temp.c | ||
| time.c | ||
| traps.c | ||
| vecemu.c | ||
| vector.S | ||
| vmlinux.lds.S | ||