Akash Goel f4e9af4f5a drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set ... So far PM IER/IIR/IMR registers were being used only for Turbo related interrupts. But interrupts coming from GuC also use the same set. As a precursor to supporting GuC interrupts, added new low level routines so as to allow sharing the programming of PM IER/IIR/IMR registers between Turbo & GuC. Also similar to PM IMR, maintaining a bitmask for PM IER register, to allow easy sharing of it between Turbo & GuC without involving a rmw operation. v2: - For appropriateness & avoid any ambiguity, rename old functions enable/disable pm_irq to mask/unmask pm_irq and rename new functions enable/disable pm_interrupts to enable/disable pm_irq. (Tvrtko) - Use u32 in place of uint32_t. (Tvrtko) v3: - Rename the fields pm_irq_mask & pm_ier_mask and do some cleanup. (Chris) - Rebase. v4: Fix the inadvertent disabling of User interrupt for VECS ring causing failure for certain IGTs. v5: Use dev_priv with HAS_VEBOX macro. (Tvrtko) Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Akash Goel <akash.goel@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>		2016-10-25 09:34:06 +01:00
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drm	drm/i915: Add low level set of routines for programming PM IER/IIR/IMR register set	2016-10-25 09:34:06 +01:00
host1x	drm/tegra: dsi: Enhance runtime power management	2016-08-24 15:58:57 +02:00
ipu-v3	gpu: Remove depends on RESET_CONTROLLER when not a provider	2016-10-19 09:26:15 +02:00
vga	drivers/gpu/vga: allocate vga_arb_write() buffer on stack	2016-10-17 08:21:14 +02:00
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