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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c21ac06648
The common clk implementation for MMP broke without anyone noticing
when we stopped including linux/clk.h from the clk-provider header.
This did not show up in the defconfig builds because those use the
legacy MMP clk drivers, and it did not show up in my randconfig tests
either because I was testing with my mmp multiplatform series
applied, which at some point gained the fixup.
This fixes the three broken files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 61ae76563e ("clk: Remove clk.h from clk-provider.h")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
331 lines
11 KiB
C
331 lines
11 KiB
C
/*
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* pxa910 clock framework source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <mach/addr-map.h>
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#include "clk.h"
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#define APBC_RTC 0x28
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#define APBC_TWSI0 0x2c
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#define APBC_KPC 0x18
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#define APBC_UART0 0x0
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#define APBC_UART1 0x4
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#define APBC_GPIO 0x8
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#define APBC_PWM0 0xc
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#define APBC_PWM1 0x10
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#define APBC_PWM2 0x14
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#define APBC_PWM3 0x18
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#define APBC_SSP0 0x1c
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#define APBC_SSP1 0x20
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#define APBC_SSP2 0x4c
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#define APBCP_TWSI1 0x28
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#define APBCP_UART2 0x1c
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#define APMU_SDH0 0x54
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#define APMU_SDH1 0x58
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#define APMU_USB 0x5c
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#define APMU_DISP0 0x4c
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#define APMU_CCIC0 0x50
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#define APMU_DFC 0x60
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#define MPMU_UART_PLL 0x14
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static DEFINE_SPINLOCK(clk_lock);
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static struct mmp_clk_factor_masks uart_factor_masks = {
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.factor = 2,
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.num_mask = 0x1fff,
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.den_mask = 0x1fff,
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.num_shift = 16,
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.den_shift = 0,
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};
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static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
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{.num = 8125, .den = 1536}, /*14.745MHZ */
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};
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static const char *uart_parent[] = {"pll1_3_16", "uart_pll"};
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static const char *ssp_parent[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"};
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static const char *sdh_parent[] = {"pll1_12", "pll1_13"};
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static const char *disp_parent[] = {"pll1_2", "pll1_12"};
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static const char *ccic_parent[] = {"pll1_2", "pll1_12"};
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static const char *ccic_phy_parent[] = {"pll1_6", "pll1_12"};
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void __init pxa910_clk_init(void)
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{
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struct clk *clk;
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struct clk *uart_pll;
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void __iomem *mpmu_base;
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void __iomem *apmu_base;
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void __iomem *apbcp_base;
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void __iomem *apbc_base;
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mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
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if (mpmu_base == NULL) {
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pr_err("error to ioremap MPMU base\n");
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return;
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}
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apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
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if (apmu_base == NULL) {
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pr_err("error to ioremap APMU base\n");
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return;
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}
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apbcp_base = ioremap(APB_PHYS_BASE + 0x3b000, SZ_4K);
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if (apbcp_base == NULL) {
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pr_err("error to ioremap APBC extension base\n");
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return;
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}
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apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
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if (apbc_base == NULL) {
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pr_err("error to ioremap APBC base\n");
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return;
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}
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clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
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clk_register_clkdev(clk, "clk32", NULL);
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clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
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26000000);
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clk_register_clkdev(clk, "vctcxo", NULL);
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clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
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624000000);
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clk_register_clkdev(clk, "pll1", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_2", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_4", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_8", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_16", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2",
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CLK_SET_RATE_PARENT, 1, 3);
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clk_register_clkdev(clk, "pll1_6", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_12", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_24", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_48", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_96", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1",
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CLK_SET_RATE_PARENT, 1, 13);
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clk_register_clkdev(clk, "pll1_13", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1",
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CLK_SET_RATE_PARENT, 2, 3);
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clk_register_clkdev(clk, "pll1_13_1_5", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1",
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CLK_SET_RATE_PARENT, 2, 3);
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clk_register_clkdev(clk, "pll1_2_1_5", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1",
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CLK_SET_RATE_PARENT, 3, 16);
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clk_register_clkdev(clk, "pll1_3_16", NULL);
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uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
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mpmu_base + MPMU_UART_PLL,
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&uart_factor_masks, uart_factor_tbl,
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ARRAY_SIZE(uart_factor_tbl), &clk_lock);
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clk_set_rate(uart_pll, 14745600);
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clk_register_clkdev(uart_pll, "uart_pll", NULL);
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clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5",
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apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
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clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5",
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apbcp_base + APBCP_TWSI1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
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clk = mmp_clk_register_apbc("gpio", "vctcxo",
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apbc_base + APBC_GPIO, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-gpio");
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clk = mmp_clk_register_apbc("kpc", "clk32",
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apbc_base + APBC_KPC, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa27x-keypad");
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clk = mmp_clk_register_apbc("rtc", "clk32",
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apbc_base + APBC_RTC, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "sa1100-rtc");
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clk = mmp_clk_register_apbc("pwm0", "pll1_48",
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apbc_base + APBC_PWM0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa910-pwm.0");
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clk = mmp_clk_register_apbc("pwm1", "pll1_48",
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apbc_base + APBC_PWM1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa910-pwm.1");
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clk = mmp_clk_register_apbc("pwm2", "pll1_48",
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apbc_base + APBC_PWM2, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa910-pwm.2");
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clk = mmp_clk_register_apbc("pwm3", "pll1_48",
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apbc_base + APBC_PWM3, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
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clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, uart_pll);
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clk_register_clkdev(clk, "uart_mux.0", NULL);
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clk = mmp_clk_register_apbc("uart0", "uart0_mux",
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apbc_base + APBC_UART0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
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clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, uart_pll);
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clk_register_clkdev(clk, "uart_mux.1", NULL);
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clk = mmp_clk_register_apbc("uart1", "uart1_mux",
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apbc_base + APBC_UART1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
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clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, uart_pll);
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clk_register_clkdev(clk, "uart_mux.2", NULL);
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clk = mmp_clk_register_apbc("uart2", "uart2_mux",
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apbcp_base + APBCP_UART2, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
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clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
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ARRAY_SIZE(ssp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
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clk_register_clkdev(clk, "uart_mux.0", NULL);
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clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
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apbc_base + APBC_SSP0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-ssp.0");
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clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
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ARRAY_SIZE(ssp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
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clk_register_clkdev(clk, "ssp_mux.1", NULL);
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clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
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apbc_base + APBC_SSP1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-ssp.1");
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clk = mmp_clk_register_apmu("dfc", "pll1_4",
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apmu_base + APMU_DFC, 0x19b, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
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clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
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ARRAY_SIZE(sdh_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
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clk_register_clkdev(clk, "sdh0_mux", NULL);
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clk = mmp_clk_register_apmu("sdh0", "sdh_mux",
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apmu_base + APMU_SDH0, 0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
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clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
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ARRAY_SIZE(sdh_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
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clk_register_clkdev(clk, "sdh1_mux", NULL);
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clk = mmp_clk_register_apmu("sdh1", "sdh1_mux",
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apmu_base + APMU_SDH1, 0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "sdhci-pxa.1");
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clk = mmp_clk_register_apmu("usb", "usb_pll",
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apmu_base + APMU_USB, 0x9, &clk_lock);
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clk_register_clkdev(clk, "usb_clk", NULL);
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clk = mmp_clk_register_apmu("sph", "usb_pll",
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apmu_base + APMU_USB, 0x12, &clk_lock);
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clk_register_clkdev(clk, "sph_clk", NULL);
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clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
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ARRAY_SIZE(disp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
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clk_register_clkdev(clk, "disp_mux.0", NULL);
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clk = mmp_clk_register_apmu("disp0", "disp0_mux",
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apmu_base + APMU_DISP0, 0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-disp.0");
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clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
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ARRAY_SIZE(ccic_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
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clk_register_clkdev(clk, "ccic_mux.0", NULL);
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clk = mmp_clk_register_apmu("ccic0", "ccic0_mux",
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apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
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clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
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clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
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ARRAY_SIZE(ccic_phy_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
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clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
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clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
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apmu_base + APMU_CCIC0, 0x24, &clk_lock);
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clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
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clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux",
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CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
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10, 5, 0, &clk_lock);
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clk_register_clkdev(clk, "sphyclk_div", NULL);
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clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
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apmu_base + APMU_CCIC0, 0x300, &clk_lock);
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clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
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}
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