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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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19d863446a
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
95 lines
2.3 KiB
C
95 lines
2.3 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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/**
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* struct clk_gate_exclusive - i.MX specific gate clock which is mutually
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* exclusive with other gate clocks
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*
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* @gate: the parent class
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* @exclusive_mask: mask of gate bits which are mutually exclusive to this
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* gate clock
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*
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* The imx exclusive gate clock is a subclass of basic clk_gate
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* with an addtional mask to indicate which other gate bits in the same
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* register is mutually exclusive to this gate clock.
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*/
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struct clk_gate_exclusive {
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struct clk_gate gate;
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u32 exclusive_mask;
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};
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static int clk_gate_exclusive_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
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struct clk_gate_exclusive *exgate = container_of(gate,
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struct clk_gate_exclusive, gate);
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u32 val = readl(gate->reg);
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if (val & exgate->exclusive_mask)
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return -EBUSY;
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return clk_gate_ops.enable(hw);
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}
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static void clk_gate_exclusive_disable(struct clk_hw *hw)
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{
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clk_gate_ops.disable(hw);
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}
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static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
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{
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return clk_gate_ops.is_enabled(hw);
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}
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static const struct clk_ops clk_gate_exclusive_ops = {
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.enable = clk_gate_exclusive_enable,
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.disable = clk_gate_exclusive_disable,
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.is_enabled = clk_gate_exclusive_is_enabled,
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};
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struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u32 exclusive_mask)
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{
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struct clk_gate_exclusive *exgate;
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struct clk_gate *gate;
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struct clk *clk;
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struct clk_init_data init;
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if (exclusive_mask == 0)
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return ERR_PTR(-EINVAL);
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exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
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if (!exgate)
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return ERR_PTR(-ENOMEM);
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gate = &exgate->gate;
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init.name = name;
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init.ops = &clk_gate_exclusive_ops;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = parent ? &parent : NULL;
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init.num_parents = parent ? 1 : 0;
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gate->reg = reg;
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gate->bit_idx = shift;
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gate->lock = &imx_ccm_lock;
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gate->hw.init = &init;
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exgate->exclusive_mask = exclusive_mask;
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clk = clk_register(NULL, &gate->hw);
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if (IS_ERR(clk))
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kfree(exgate);
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return clk;
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}
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