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4b91428699
8xx uses a two level page table with two different linux page size support (4k and 16k). 8xx also support two different hugepage sizes 512k and 8M. In order to support them on linux we define two different page table layout. The size of pages is in the PGD entry, using PS field (bits 28-29): 00 : Small pages (4k or 16k) 01 : 512k pages 10 : reserved 11 : 8M pages For 512K hugepage size a pgd entry have the below format [<hugepte address >0101] . The hugepte table allocated will contain 8 entries pointing to 512K huge pte in 4k pages mode and 64 entries in 16k pages mode. For 8M in 16k mode, a pgd entry have the below format [<hugepte address >1101] . The hugepte table allocated will contain 8 entries pointing to 8M huge pte. For 8M in 4k mode, multiple pgd entries point to the same hugepte address and pgd entry will have the below format [<hugepte address>1101]. The hugepte table allocated will only have one entry. For the time being, we do not support CPU15 ERRATA when HUGETLB is selected Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> (v3, for the generic bits) Signed-off-by: Scott Wood <oss@buserror.net>
140 lines
4.7 KiB
C
140 lines
4.7 KiB
C
/*
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* Contains register definitions common to PowerPC 8xx CPUs. Notice
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*/
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#ifndef _ASM_POWERPC_REG_8xx_H
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#define _ASM_POWERPC_REG_8xx_H
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#include <asm/mmu.h>
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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#define SPRN_IC_CST 560 /* Instruction cache control/status */
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#define SPRN_IC_ADR 561 /* Address needed for some commands */
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#define SPRN_IC_DAT 562 /* Read-only data register */
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#define SPRN_DC_CST 568 /* Data cache control/status */
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#define SPRN_DC_ADR 569 /* Address needed for some commands */
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#define SPRN_DC_DAT 570 /* Read-only data register */
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/* Misc Debug */
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#define SPRN_DPDR 630
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#define SPRN_MI_CAM 816
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#define SPRN_MI_RAM0 817
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#define SPRN_MI_RAM1 818
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#define SPRN_MD_CAM 824
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#define SPRN_MD_RAM0 825
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#define SPRN_MD_RAM1 826
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/* Special MSR manipulation registers */
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#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */
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#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
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/* Commands. Only the first few are available to the instruction cache.
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*/
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#define IDC_ENABLE 0x02000000 /* Cache enable */
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#define IDC_DISABLE 0x04000000 /* Cache disable */
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#define IDC_LDLCK 0x06000000 /* Load and lock */
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#define IDC_UNLINE 0x08000000 /* Unlock line */
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#define IDC_UNALL 0x0a000000 /* Unlock all */
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#define IDC_INVALL 0x0c000000 /* Invalidate all */
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#define DC_FLINE 0x0e000000 /* Flush data cache line */
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#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
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#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
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#define DC_SLES 0x05000000 /* Set little endian swap mode */
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#define DC_CLES 0x07000000 /* Clear little endian swap mode */
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/* Status.
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*/
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#define IDC_ENABLED 0x80000000 /* Cache is enabled */
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#define IDC_CERR1 0x00200000 /* Cache error 1 */
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#define IDC_CERR2 0x00100000 /* Cache error 2 */
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#define IDC_CERR3 0x00080000 /* Cache error 3 */
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#define DC_DFWT 0x40000000 /* Data cache is forced write through */
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#define DC_LES 0x20000000 /* Caches are little endian mode */
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#ifdef CONFIG_8xx_CPU6
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#define do_mtspr_cpu6(rn, rn_addr, v) \
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do { \
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int _reg_cpu6 = rn_addr, _tmp_cpu6; \
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asm volatile("stw %0, %1;" \
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"lwz %0, %1;" \
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"mtspr " __stringify(rn) ",%2" : \
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: "r" (_reg_cpu6), "m"(_tmp_cpu6), \
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"r" ((unsigned long)(v)) \
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: "memory"); \
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} while (0)
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#define do_mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : \
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: "r" ((unsigned long)(v)) \
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: "memory")
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#define mtspr(rn, v) \
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do { \
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if (rn == SPRN_IMMR) \
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do_mtspr_cpu6(rn, 0x3d30, v); \
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else if (rn == SPRN_IC_CST) \
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do_mtspr_cpu6(rn, 0x2110, v); \
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else if (rn == SPRN_IC_ADR) \
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do_mtspr_cpu6(rn, 0x2310, v); \
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else if (rn == SPRN_IC_DAT) \
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do_mtspr_cpu6(rn, 0x2510, v); \
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else if (rn == SPRN_DC_CST) \
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do_mtspr_cpu6(rn, 0x3110, v); \
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else if (rn == SPRN_DC_ADR) \
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do_mtspr_cpu6(rn, 0x3310, v); \
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else if (rn == SPRN_DC_DAT) \
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do_mtspr_cpu6(rn, 0x3510, v); \
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else if (rn == SPRN_MI_CTR) \
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do_mtspr_cpu6(rn, 0x2180, v); \
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else if (rn == SPRN_MI_AP) \
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do_mtspr_cpu6(rn, 0x2580, v); \
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else if (rn == SPRN_MI_EPN) \
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do_mtspr_cpu6(rn, 0x2780, v); \
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else if (rn == SPRN_MI_TWC) \
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do_mtspr_cpu6(rn, 0x2b80, v); \
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else if (rn == SPRN_MI_RPN) \
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do_mtspr_cpu6(rn, 0x2d80, v); \
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else if (rn == SPRN_MI_CAM) \
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do_mtspr_cpu6(rn, 0x2190, v); \
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else if (rn == SPRN_MI_RAM0) \
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do_mtspr_cpu6(rn, 0x2390, v); \
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else if (rn == SPRN_MI_RAM1) \
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do_mtspr_cpu6(rn, 0x2590, v); \
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else if (rn == SPRN_MD_CTR) \
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do_mtspr_cpu6(rn, 0x3180, v); \
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else if (rn == SPRN_M_CASID) \
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do_mtspr_cpu6(rn, 0x3380, v); \
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else if (rn == SPRN_MD_AP) \
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do_mtspr_cpu6(rn, 0x3580, v); \
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else if (rn == SPRN_MD_EPN) \
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do_mtspr_cpu6(rn, 0x3780, v); \
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else if (rn == SPRN_M_TWB) \
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do_mtspr_cpu6(rn, 0x3980, v); \
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else if (rn == SPRN_MD_TWC) \
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do_mtspr_cpu6(rn, 0x3b80, v); \
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else if (rn == SPRN_MD_RPN) \
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do_mtspr_cpu6(rn, 0x3d80, v); \
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else if (rn == SPRN_M_TW) \
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do_mtspr_cpu6(rn, 0x3f80, v); \
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else if (rn == SPRN_MD_CAM) \
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do_mtspr_cpu6(rn, 0x3190, v); \
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else if (rn == SPRN_MD_RAM0) \
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do_mtspr_cpu6(rn, 0x3390, v); \
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else if (rn == SPRN_MD_RAM1) \
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do_mtspr_cpu6(rn, 0x3590, v); \
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else if (rn == SPRN_DEC) \
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do_mtspr_cpu6(rn, 0x2c00, v); \
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else if (rn == SPRN_TBWL) \
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do_mtspr_cpu6(rn, 0x3880, v); \
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else if (rn == SPRN_TBWU) \
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do_mtspr_cpu6(rn, 0x3a80, v); \
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else if (rn == SPRN_DPDR) \
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do_mtspr_cpu6(rn, 0x2d30, v); \
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else \
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do_mtspr(rn, v); \
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} while (0)
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#endif
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#endif /* _ASM_POWERPC_REG_8xx_H */
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