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f4be3c67ed
Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on Venice2 and Jetson TK1. This also enables support for the PMU hardware found on Tegra124, which among other things, can be used for performance measurements. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJV11X7AAoJEN0jrNd/PrOhbK0QAKOb9gae0PiwFojQ0IJZz78N 5kg8IlQLBzxukpGGKtR37qInADBXQkdOlPtxfylQPjm0eZSy96bU94uJlVcg4oUU SkbN1yr0TFu1VxkMcnfTD6VwQnqSlX4NwBlDHUMp1an9e6EnZjyf2Hlo5gp7RtNb 1ZH/ywObb+yW+sRjczSDMqcM/qtKlOALGNFE8+EKA1MA2aECbm+AyEZr2n5VH6jx tXOeMVwDLgHUe4ty2obs+srbMBzXc3hZMzsmC9kKspermd8I2ERErubAW+WT2k7D eplih+e/MBRPzdBc3Hhi5QeYxmOHtQDEB5AcYEskpZsFj2S6xzOrQtcDbBIn0QX9 RegpLQyfTDQ42Jk1wcFz264ffFKTl8JSqkHHH5U7MvECt4qvbXVo/Kbkiytz3g7J SCFHmFXRKG4Snm47+UapPBOqb4nIUvNMIOJZDDLSmIX32r65vrBZG+2WNSOfewXZ Im0E6Mcqsi4JYvpStUmQkIEJaqDoZFPADwi66HpXc8ShE+ekF+OWi8QYwsL4qYbU 4D1SbZuMN21sxav4uxXo6DIIEY45/JRPCnXki2CZv8Qi21PyQQ3Q/Jv3TC7Sa81o kgEnvfO7Ekn+j4+Jpr3zFBcq+eH/dVOcdqWswkdbCHMZ1jDlq+eK3tHVl3f2BvlK JJqRij4XpFXRADYaoSut =tdwi -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt ARM: tegra: Devicetree changes for v4.3-rc1 Enables CPU frequency scaling on Jetson TK1 and enables the GK20A GPU on Venice2 and Jetson TK1. This also enables support for the PMU hardware found on Tegra124, which among other things, can be used for performance measurements. * tag 'tegra-for-4.3-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree pinctrl: tegra: Only set the gpio range if needed clk: tegra: Add the DFLL as a possible parent of the cclk_g clock clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend clk: tegra: Add Tegra124 DFLL clocksource platform driver clk: tegra: Add DFLL DVCO reset control for Tegra124 clk: tegra: Introduce ability for SoC-specific reset control callbacks clk: tegra: Add functions for parsing CVB tables clk: tegra: Add closed loop support for the DFLL clk: tegra: Add library for the DFLL clock source (open-loop mode) clk: tegra: Add binding for the Tegra124 DFLL clocksource Signed-off-by: Olof Johansson <olof@lixom.net> |
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| arm | ||
| clk | ||
| clock | ||
| dma | ||
| gpio | ||
| iio | ||
| input | ||
| interrupt-controller | ||
| leds | ||
| media | ||
| memory | ||
| mfd | ||
| net | ||
| phy | ||
| pinctrl | ||
| pwm | ||
| regulator | ||
| reset | ||
| reset-controller | ||
| soc | ||
| sound | ||
| spmi | ||
| thermal | ||