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linux_dsm_epyc7002/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
Linus Torvalds eb275167d1 ARM: Device-tree updates 
As always, the bulk of updates. Some of the news this cycle:
 
 New SoC descriptions:
  - Broadcom BCM2711
  - Amlogic Meson A1 and G12
  - Freescale S32V234
  - Marvell Armada AP807/AP807-quad and CP115
  - Realtek RTD1293 and RTD1296
  - Rockchip RK3308
 
 New boards and platforms:
  - Allwinner: NanoPi Duo2
  - Amlogic: Ugoos am6
  - Atmel at91: Overkiz Kizbox2/4
  - Broadcom: RPi4, Luxul XWC-2000
  - Marvell: New Espressobin flavor
  - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix
    E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and
    OPOS6ULDev
  - Renesas: Salvator-XS
  - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Device-tree updates from Olof Johansson:
 "As always, the bulk of updates.  Some of the news this cycle:

  New SoC descriptions:
   - Broadcom BCM2711
   - Amlogic Meson A1 and G12
   - Freescale S32V234
   - Marvell Armada AP807/AP807-quad and CP115
   - Realtek RTD1293 and RTD1296
   - Rockchip RK3308

  New boards and platforms:
   - Allwinner: NanoPi Duo2
   - Amlogic: Ugoos am6
   - Atmel at91: Overkiz Kizbox2/4
   - Broadcom: RPi4, Luxul XWC-2000
   - Marvell: New Espressobin flavor
   - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix
     E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and
     OPOS6ULDev
   - Renesas: Salvator-XS
   - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits)
  ARM: dts: logicpd-torpedo: Disable USB Host
  arm: dts: mt6323: add keys, power-controller, rtc and codec
  arm64: dts: mt8183: add systimer0 device node
  dt-bindings: mediatek: update bindings for MT8183 systimer
  arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc
  arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board.
  arm64: dts: rockchip: Add Beelink A1
  dt-bindings: ARM: rockchip: Add Beelink A1
  arm64: dts: rockchip: Add RK3328 audio pipelines
  arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports
  arm64: dts: ti: k3-j721e-main: add USB controller nodes
  ARM: dts: aspeed-g6: Add timer description
  ARM: dts: aspeed: ast2600evb: Enable i2c buses
  ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards
  dt-bindings: arm: at91: Document Kizbox2-2 board binding
  arm64: dts: meson-gx: fix i2c compatible
  arm64: dts: meson-gx: cec node should be disabled by default
  arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible
  arm64: dts: meson-gxm: fix gpu irq order
  arm64: dts: meson-g12a: fix gpu irq order
  ...
2019-12-05 12:09:47 -08:00

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for CZ.NIC Turris Mox Board
* 2019 by Marek Behun <marek.behun@nic.cz>
*/
/dts-v1/;
#include <dt-bindings/bus/moxtet.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "armada-372x.dtsi"
/ {
model = "CZ.NIC Turris Mox Board";
compatible = "cznic,turris-mox", "marvell,armada3720",
"marvell,armada3710";
aliases {
spi0 = &spi0;
ethernet1 = &eth1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
red {
label = "mox:red:activity";
gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
exp_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
};
vsdc_reg: vsdc-reg {
compatible = "regulator-gpio";
regulator-name = "vsdc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
vsdio_reg: vsdio-reg {
compatible = "regulator-gpio";
regulator-name = "vsdio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
states = <1800000 0x1
3300000 0x0>;
enable-active-high;
};
sdhci1_pwrseq: sdhci1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
status = "okay";
};
sfp: sfp {
compatible = "sff,sfp+";
i2c-bus = <&i2c0>;
los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
/* enabled by U-Boot if SFP module is present */
status = "disabled";
};
firmware {
turris-mox-rwtm {
compatible = "cznic,turris-mox-rwtm";
mboxes = <&rwtm 0>;
status = "okay";
};
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <100000>;
status = "okay";
rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};
&pcie_reset_pins {
function = "gpio";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
status = "okay";
max-link-speed = <2>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
phys = <&comphy1 0>;
/* enabled by U-Boot if PCIe module is present */
status = "disabled";
};
&uart0 {
status = "okay";
};
&eth0 {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii-id";
phy = <&phy1>;
status = "okay";
};
&eth1 {
phy-mode = "2500base-x";
managed = "in-band-status";
phys = <&comphy0 1>;
};
&sdhci0 {
wp-inverted;
bus-width = <4>;
cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
vqmmc-supply = <&vsdc_reg>;
marvell,pad-type = "sd";
status = "okay";
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&sdio_pins>;
non-removable;
bus-width = <4>;
marvell,pad-type = "sd";
vqmmc-supply = <&vsdio_reg>;
mmc-pwrseq = <&sdhci1_pwrseq>;
status = "okay";
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
assigned-clocks = <&nb_periph_clk 7>;
assigned-clock-parents = <&tbg 1>;
assigned-clock-rates = <20000000>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "secure-firmware";
reg = <0x0 0x20000>;
};
partition@20000 {
label = "u-boot";
reg = <0x20000 0x160000>;
};
partition@180000 {
label = "u-boot-env";
reg = <0x180000 0x10000>;
};
partition@190000 {
label = "Rescue system";
reg = <0x190000 0x660000>;
};
partition@7f0000 {
label = "dtb";
reg = <0x7f0000 0x10000>;
};
};
};
moxtet: moxtet@1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "cznic,moxtet";
reg = <1>;
reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
spi-max-frequency = <10000000>;
spi-cpol;
spi-cpha;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gpiosb>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
moxtet_sfp: gpio@0 {
compatible = "cznic,moxtet-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
status = "disabled";
};
};
};
&usb2 {
status = "okay";
};
&comphy2 {
connector {
compatible = "usb-a-connector";
phy-supply = <&exp_usb3_vbus>;
};
};
&usb3 {
status = "okay";
phys = <&comphy2 0>;
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&smi_pins>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
/* switch nodes are enabled by U-Boot if modules are present */
switch0@10 {
compatible = "marvell,mv88e6190";
reg = <0x10 0>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_PERIDOT(0)>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
port@5 {
reg = <0x5>;
label = "lan5";
phy-handle = <&switch0phy5>;
};
port@6 {
reg = <0x6>;
label = "lan6";
phy-handle = <&switch0phy6>;
};
port@7 {
reg = <0x7>;
label = "lan7";
phy-handle = <&switch0phy7>;
};
port@8 {
reg = <0x8>;
label = "lan8";
phy-handle = <&switch0phy8>;
};
port@9 {
reg = <0x9>;
label = "cpu";
ethernet = <&eth1>;
phy-mode = "2500base-x";
managed = "in-band-status";
};
switch0port10: port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch1port9 &switch2port9>;
status = "disabled";
};
port-sfp@a {
reg = <0xa>;
label = "sfp";
sfp = <&sfp>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "disabled";
};
};
};
switch0@2 {
compatible = "marvell,mv88e6085";
reg = <0x2 0>;
dsa,member = <0 0>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_TOPAZ>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1_topaz: switch0phy1@11 {
reg = <0x11>;
};
switch0phy2_topaz: switch0phy2@12 {
reg = <0x12>;
};
switch0phy3_topaz: switch0phy3@13 {
reg = <0x13>;
};
switch0phy4_topaz: switch0phy4@14 {
reg = <0x14>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1_topaz>;
};
port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2_topaz>;
};
port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3_topaz>;
};
port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4_topaz>;
};
port@5 {
reg = <0x5>;
label = "cpu";
phy-mode = "2500base-x";
managed = "in-band-status";
ethernet = <&eth1>;
};
};
};
switch1@11 {
compatible = "marvell,mv88e6190";
reg = <0x11 0>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_PERIDOT(1)>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy1: switch1phy1@1 {
reg = <0x1>;
};
switch1phy2: switch1phy2@2 {
reg = <0x2>;
};
switch1phy3: switch1phy3@3 {
reg = <0x3>;
};
switch1phy4: switch1phy4@4 {
reg = <0x4>;
};
switch1phy5: switch1phy5@5 {
reg = <0x5>;
};
switch1phy6: switch1phy6@6 {
reg = <0x6>;
};
switch1phy7: switch1phy7@7 {
reg = <0x7>;
};
switch1phy8: switch1phy8@8 {
reg = <0x8>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1>;
};
port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2>;
};
port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3>;
};
port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4>;
};
port@5 {
reg = <0x5>;
label = "lan13";
phy-handle = <&switch1phy5>;
};
port@6 {
reg = <0x6>;
label = "lan14";
phy-handle = <&switch1phy6>;
};
port@7 {
reg = <0x7>;
label = "lan15";
phy-handle = <&switch1phy7>;
};
port@8 {
reg = <0x8>;
label = "lan16";
phy-handle = <&switch1phy8>;
};
switch1port9: port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch0port10>;
};
switch1port10: port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch2port9>;
status = "disabled";
};
port-sfp@a {
reg = <0xa>;
label = "sfp";
sfp = <&sfp>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "disabled";
};
};
};
switch1@2 {
compatible = "marvell,mv88e6085";
reg = <0x2 0>;
dsa,member = <0 1>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_TOPAZ>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy1_topaz: switch1phy1@11 {
reg = <0x11>;
};
switch1phy2_topaz: switch1phy2@12 {
reg = <0x12>;
};
switch1phy3_topaz: switch1phy3@13 {
reg = <0x13>;
};
switch1phy4_topaz: switch1phy4@14 {
reg = <0x14>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1_topaz>;
};
port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2_topaz>;
};
port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3_topaz>;
};
port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4_topaz>;
};
port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch0port10>;
};
};
};
switch2@12 {
compatible = "marvell,mv88e6190";
reg = <0x12 0>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_PERIDOT(2)>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch2phy1: switch2phy1@1 {
reg = <0x1>;
};
switch2phy2: switch2phy2@2 {
reg = <0x2>;
};
switch2phy3: switch2phy3@3 {
reg = <0x3>;
};
switch2phy4: switch2phy4@4 {
reg = <0x4>;
};
switch2phy5: switch2phy5@5 {
reg = <0x5>;
};
switch2phy6: switch2phy6@6 {
reg = <0x6>;
};
switch2phy7: switch2phy7@7 {
reg = <0x7>;
};
switch2phy8: switch2phy8@8 {
reg = <0x8>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1>;
};
port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2>;
};
port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3>;
};
port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4>;
};
port@5 {
reg = <0x5>;
label = "lan21";
phy-handle = <&switch2phy5>;
};
port@6 {
reg = <0x6>;
label = "lan22";
phy-handle = <&switch2phy6>;
};
port@7 {
reg = <0x7>;
label = "lan23";
phy-handle = <&switch2phy7>;
};
port@8 {
reg = <0x8>;
label = "lan24";
phy-handle = <&switch2phy8>;
};
switch2port9: port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch1port10 &switch0port10>;
};
port-sfp@a {
reg = <0xa>;
label = "sfp";
sfp = <&sfp>;
phy-mode = "sgmii";
managed = "in-band-status";
status = "disabled";
};
};
};
switch2@2 {
compatible = "marvell,mv88e6085";
reg = <0x2 0>;
dsa,member = <0 2>;
interrupt-parent = <&moxtet>;
interrupts = <MOXTET_IRQ_TOPAZ>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch2phy1_topaz: switch2phy1@11 {
reg = <0x11>;
};
switch2phy2_topaz: switch2phy2@12 {
reg = <0x12>;
};
switch2phy3_topaz: switch2phy3@13 {
reg = <0x13>;
};
switch2phy4_topaz: switch2phy4@14 {
reg = <0x14>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1_topaz>;
};
port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2_topaz>;
};
port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3_topaz>;
};
port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4_topaz>;
};
port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
managed = "in-band-status";
link = <&switch1port10 &switch0port10>;
};
};
};
};
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