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9e1b7498d7
Implement a custom reset function for the HDQ1W IP block. This is because the HDQ1W IP block, like I2C, has an internal clock gating bit that needs to be toggled after setting the SOFTRESET bit to allow the reset to propagate. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Cc: Avinash.H.M <avinashhm@ti.com> Tested-by: NeilBrown <neilb@suse.de>
73 lines
2.3 KiB
C
73 lines
2.3 KiB
C
/*
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* IP block integration code for the HDQ1W/1-wire IP block
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
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* Avinash.H.M <avinashhm@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#include <plat/omap_hwmod.h>
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#include <plat/hdq1w.h>
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#include "common.h"
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/* Maximum microseconds to wait for OMAP module to softreset */
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#define MAX_MODULE_SOFTRESET_WAIT 10000
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/**
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* omap_hdq1w_reset - reset the OMAP HDQ1W module
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* @oh: struct omap_hwmod *
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*
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* OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
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* Software Reset" of the OMAP34xx Technical Reference Manual Revision
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* ZR (SWPU223R) does not include the rather important fact that, for
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* the reset to succeed, the HDQ1W module's internal clock gate must be
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* programmed to allow the clock to propagate to the rest of the
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* module. In this sense, it's rather similar to the I2C custom reset
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* function. Returns 0.
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*/
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int omap_hdq1w_reset(struct omap_hwmod *oh)
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{
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u32 v;
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Enable the module's internal clocks */
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v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
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v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
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omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh,
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oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warning("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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return 0;
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}
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