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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4a6180ea73
This is the initial codec driver for rt5514. The codec includes a low power DSP for voice wake up. The register address is incremental by 4 in the DSP memory map. In order to recover the codec settings in the codec mode and manipulate the DSP mode for voice wake up, we use the multi-level register map. One is for ALSA API in codec mode that can be recovered by cache before recording. Another is for DSP related settings that can be accessed with 32bit address of the DSP in the application of voice wake up. Signed-off-by: Oder Chiou <oder_chiou@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
253 lines
8.2 KiB
C
253 lines
8.2 KiB
C
/*
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* rt5514.h -- RT5514 ALSA SoC audio driver
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*
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* Copyright 2015 Realtek Microelectronics
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* Author: Oder Chiou <oder_chiou@realtek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __RT5514_H__
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#define __RT5514_H__
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#define RT5514_DEVICE_ID 0x10ec5514
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#define RT5514_RESET 0x2000
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#define RT5514_PWR_ANA1 0x2004
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#define RT5514_PWR_ANA2 0x2008
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#define RT5514_I2S_CTRL1 0x2010
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#define RT5514_I2S_CTRL2 0x2014
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#define RT5514_VAD_CTRL6 0x2030
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#define RT5514_EXT_VAD_CTRL 0x206c
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#define RT5514_DIG_IO_CTRL 0x2070
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#define RT5514_PAD_CTRL1 0x2080
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#define RT5514_DMIC_DATA_CTRL 0x20a0
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#define RT5514_DIG_SOURCE_CTRL 0x20a4
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#define RT5514_SRC_CTRL 0x20ac
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#define RT5514_DOWNFILTER2_CTRL1 0x20d0
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#define RT5514_PLL_SOURCE_CTRL 0x2100
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#define RT5514_CLK_CTRL1 0x2104
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#define RT5514_CLK_CTRL2 0x2108
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#define RT5514_PLL3_CALIB_CTRL1 0x2110
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#define RT5514_PLL3_CALIB_CTRL5 0x2124
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#define RT5514_DELAY_BUF_CTRL1 0x2140
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#define RT5514_DELAY_BUF_CTRL3 0x2148
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#define RT5514_DOWNFILTER0_CTRL1 0x2190
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#define RT5514_DOWNFILTER0_CTRL2 0x2194
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#define RT5514_DOWNFILTER0_CTRL3 0x2198
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#define RT5514_DOWNFILTER1_CTRL1 0x21a0
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#define RT5514_DOWNFILTER1_CTRL2 0x21a4
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#define RT5514_DOWNFILTER1_CTRL3 0x21a8
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#define RT5514_ANA_CTRL_LDO10 0x2200
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#define RT5514_ANA_CTRL_LDO18_16 0x2204
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#define RT5514_ANA_CTRL_ADC12 0x2210
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#define RT5514_ANA_CTRL_ADC21 0x2214
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#define RT5514_ANA_CTRL_ADC22 0x2218
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#define RT5514_ANA_CTRL_ADC23 0x221c
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#define RT5514_ANA_CTRL_MICBST 0x2220
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#define RT5514_ANA_CTRL_ADCFED 0x2224
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#define RT5514_ANA_CTRL_INBUF 0x2228
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#define RT5514_ANA_CTRL_VREF 0x222c
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#define RT5514_ANA_CTRL_PLL3 0x2240
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#define RT5514_ANA_CTRL_PLL1_1 0x2260
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#define RT5514_ANA_CTRL_PLL1_2 0x2264
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#define RT5514_DMIC_LP_CTRL 0x2e00
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#define RT5514_MISC_CTRL_DSP 0x2e04
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#define RT5514_DSP_CTRL1 0x2f00
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#define RT5514_DSP_CTRL3 0x2f08
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#define RT5514_DSP_CTRL4 0x2f10
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#define RT5514_VENDOR_ID1 0x2ff0
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#define RT5514_VENDOR_ID2 0x2ff4
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#define RT5514_DSP_MAPPING 0x18000000
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/* RT5514_PWR_ANA1 (0x2004) */
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#define RT5514_POW_LDO18_IN (0x1 << 5)
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#define RT5514_POW_LDO18_IN_BIT 5
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#define RT5514_POW_LDO18_ADC (0x1 << 4)
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#define RT5514_POW_LDO18_ADC_BIT 4
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#define RT5514_POW_LDO21 (0x1 << 3)
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#define RT5514_POW_LDO21_BIT 3
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#define RT5514_POW_BG_LDO18_IN (0x1 << 2)
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#define RT5514_POW_BG_LDO18_IN_BIT 2
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#define RT5514_POW_BG_LDO21 (0x1 << 1)
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#define RT5514_POW_BG_LDO21_BIT 1
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/* RT5514_PWR_ANA2 (0x2008) */
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#define RT5514_POW_PLL1 (0x1 << 18)
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#define RT5514_POW_PLL1_BIT 18
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#define RT5514_POW_PLL1_LDO (0x1 << 16)
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#define RT5514_POW_PLL1_LDO_BIT 16
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#define RT5514_POW_BG_MBIAS (0x1 << 15)
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#define RT5514_POW_BG_MBIAS_BIT 15
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#define RT5514_POW_MBIAS (0x1 << 14)
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#define RT5514_POW_MBIAS_BIT 14
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#define RT5514_POW_VREF2 (0x1 << 13)
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#define RT5514_POW_VREF2_BIT 13
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#define RT5514_POW_VREF1 (0x1 << 12)
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#define RT5514_POW_VREF1_BIT 12
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#define RT5514_POWR_LDO16 (0x1 << 11)
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#define RT5514_POWR_LDO16_BIT 11
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#define RT5514_POWL_LDO16 (0x1 << 10)
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#define RT5514_POWL_LDO16_BIT 10
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#define RT5514_POW_ADC2 (0x1 << 9)
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#define RT5514_POW_ADC2_BIT 9
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#define RT5514_POW_INPUT_BUF (0x1 << 8)
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#define RT5514_POW_INPUT_BUF_BIT 8
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#define RT5514_POW_ADC1_R (0x1 << 7)
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#define RT5514_POW_ADC1_R_BIT 7
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#define RT5514_POW_ADC1_L (0x1 << 6)
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#define RT5514_POW_ADC1_L_BIT 6
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#define RT5514_POW2_BSTR (0x1 << 5)
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#define RT5514_POW2_BSTR_BIT 5
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#define RT5514_POW2_BSTL (0x1 << 4)
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#define RT5514_POW2_BSTL_BIT 4
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#define RT5514_POW_BSTR (0x1 << 3)
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#define RT5514_POW_BSTR_BIT 3
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#define RT5514_POW_BSTL (0x1 << 2)
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#define RT5514_POW_BSTL_BIT 2
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#define RT5514_POW_ADCFEDR (0x1 << 1)
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#define RT5514_POW_ADCFEDR_BIT 1
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#define RT5514_POW_ADCFEDL (0x1 << 0)
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#define RT5514_POW_ADCFEDL_BIT 0
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/* RT5514_I2S_CTRL1 (0x2010) */
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#define RT5514_TDM_MODE (0x1 << 28)
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#define RT5514_TDM_MODE_SFT 28
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#define RT5514_I2S_LR_MASK (0x1 << 26)
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#define RT5514_I2S_LR_SFT 26
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#define RT5514_I2S_LR_NOR (0x0 << 26)
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#define RT5514_I2S_LR_INV (0x1 << 26)
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#define RT5514_I2S_BP_MASK (0x1 << 25)
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#define RT5514_I2S_BP_SFT 25
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#define RT5514_I2S_BP_NOR (0x0 << 25)
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#define RT5514_I2S_BP_INV (0x1 << 25)
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#define RT5514_I2S_DF_MASK (0x7 << 16)
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#define RT5514_I2S_DF_SFT 16
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#define RT5514_I2S_DF_I2S (0x0 << 16)
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#define RT5514_I2S_DF_LEFT (0x1 << 16)
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#define RT5514_I2S_DF_PCM_A (0x2 << 16)
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#define RT5514_I2S_DF_PCM_B (0x3 << 16)
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#define RT5514_TDMSLOT_SEL_RX_MASK (0x3 << 10)
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#define RT5514_TDMSLOT_SEL_RX_SFT 10
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#define RT5514_TDMSLOT_SEL_RX_4CH (0x1 << 10)
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#define RT5514_CH_LEN_RX_MASK (0x3 << 8)
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#define RT5514_CH_LEN_RX_SFT 8
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#define RT5514_CH_LEN_RX_16 (0x0 << 8)
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#define RT5514_CH_LEN_RX_20 (0x1 << 8)
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#define RT5514_CH_LEN_RX_24 (0x2 << 8)
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#define RT5514_CH_LEN_RX_32 (0x3 << 8)
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#define RT5514_TDMSLOT_SEL_TX_MASK (0x3 << 6)
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#define RT5514_TDMSLOT_SEL_TX_SFT 6
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#define RT5514_TDMSLOT_SEL_TX_4CH (0x1 << 6)
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#define RT5514_CH_LEN_TX_MASK (0x3 << 4)
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#define RT5514_CH_LEN_TX_SFT 4
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#define RT5514_CH_LEN_TX_16 (0x0 << 4)
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#define RT5514_CH_LEN_TX_20 (0x1 << 4)
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#define RT5514_CH_LEN_TX_24 (0x2 << 4)
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#define RT5514_CH_LEN_TX_32 (0x3 << 4)
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#define RT5514_I2S_DL_MASK (0x3 << 0)
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#define RT5514_I2S_DL_SFT 0
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#define RT5514_I2S_DL_16 (0x0 << 0)
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#define RT5514_I2S_DL_20 (0x1 << 0)
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#define RT5514_I2S_DL_24 (0x2 << 0)
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#define RT5514_I2S_DL_8 (0x3 << 0)
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/* RT5514_DIG_SOURCE_CTRL (0x20a4) */
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#define RT5514_AD1_DMIC_INPUT_SEL (0x1 << 1)
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#define RT5514_AD1_DMIC_INPUT_SEL_SFT 1
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#define RT5514_AD0_DMIC_INPUT_SEL (0x1 << 0)
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#define RT5514_AD0_DMIC_INPUT_SEL_SFT 0
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/* RT5514_PLL_SOURCE_CTRL (0x2100) */
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#define RT5514_PLL_1_SEL_MASK (0x7 << 12)
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#define RT5514_PLL_1_SEL_SFT 12
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#define RT5514_PLL_1_SEL_SCLK (0x3 << 12)
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#define RT5514_PLL_1_SEL_MCLK (0x4 << 12)
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/* RT5514_CLK_CTRL1 (0x2104) */
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#define RT5514_CLK_AD_ANA1_EN (0x1 << 31)
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#define RT5514_CLK_AD_ANA1_EN_BIT 31
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#define RT5514_CLK_AD1_EN (0x1 << 24)
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#define RT5514_CLK_AD1_EN_BIT 24
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#define RT5514_CLK_AD0_EN (0x1 << 23)
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#define RT5514_CLK_AD0_EN_BIT 23
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#define RT5514_CLK_DMIC_OUT_SEL_MASK (0x7 << 8)
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#define RT5514_CLK_DMIC_OUT_SEL_SFT 8
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/* RT5514_CLK_CTRL2 (0x2108) */
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#define RT5514_CLK_SYS_DIV_OUT_MASK (0x7 << 8)
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#define RT5514_CLK_SYS_DIV_OUT_SFT 8
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#define RT5514_SEL_ADC_OSR_MASK (0x7 << 4)
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#define RT5514_SEL_ADC_OSR_SFT 4
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#define RT5514_CLK_SYS_PRE_SEL_MASK (0x3 << 0)
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#define RT5514_CLK_SYS_PRE_SEL_SFT 0
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#define RT5514_CLK_SYS_PRE_SEL_MCLK (0x2 << 0)
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#define RT5514_CLK_SYS_PRE_SEL_PLL (0x3 << 0)
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/* RT5514_DOWNFILTER_CTRL (0x2190 0x2194 0x21a0 0x21a4) */
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#define RT5514_AD_DMIC_MIX (0x1 << 11)
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#define RT5514_AD_DMIC_MIX_BIT 11
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#define RT5514_AD_AD_MIX (0x1 << 10)
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#define RT5514_AD_AD_MIX_BIT 10
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#define RT5514_AD_AD_MUTE (0x1 << 7)
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#define RT5514_AD_AD_MUTE_BIT 7
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#define RT5514_AD_GAIN_MASK (0x7f << 0)
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#define RT5514_AD_GAIN_SFT 0
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/* RT5514_ANA_CTRL_MICBST (0x2220) */
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#define RT5514_SEL_BSTL_MASK (0xf << 4)
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#define RT5514_SEL_BSTL_SFT 4
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#define RT5514_SEL_BSTR_MASK (0xf << 0)
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#define RT5514_SEL_BSTR_SFT 0
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/* RT5514_ANA_CTRL_PLL1_1 (0x2260) */
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#define RT5514_PLL_K_MAX 0x1f
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#define RT5514_PLL_K_MASK (RT5514_PLL_K_MAX << 16)
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#define RT5514_PLL_K_SFT 16
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#define RT5514_PLL_N_MAX 0x1ff
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#define RT5514_PLL_N_MASK (RT5514_PLL_N_MAX << 7)
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#define RT5514_PLL_N_SFT 4
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#define RT5514_PLL_M_MAX 0xf
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#define RT5514_PLL_M_MASK (RT5514_PLL_M_MAX << 0)
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#define RT5514_PLL_M_SFT 0
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/* RT5514_ANA_CTRL_PLL1_2 (0x2264) */
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#define RT5514_PLL_M_BP (0x1 << 2)
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#define RT5514_PLL_M_BP_SFT 2
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#define RT5514_PLL_K_BP (0x1 << 1)
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#define RT5514_PLL_K_BP_SFT 1
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#define RT5514_EN_LDO_PLL1 (0x1 << 0)
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#define RT5514_EN_LDO_PLL1_BIT 0
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#define RT5514_PLL_INP_MAX 40000000
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#define RT5514_PLL_INP_MIN 256000
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/* System Clock Source */
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enum {
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RT5514_SCLK_S_MCLK,
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RT5514_SCLK_S_PLL1,
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};
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/* PLL1 Source */
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enum {
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RT5514_PLL1_S_MCLK,
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RT5514_PLL1_S_BCLK,
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};
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struct rt5514_priv {
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struct snd_soc_codec *codec;
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struct regmap *i2c_regmap, *regmap;
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int sysclk;
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int sysclk_src;
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int lrck;
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int bclk;
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int pll_src;
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int pll_in;
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int pll_out;
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};
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#endif /* __RT5514_H__ */
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