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Earlycon calculates UART clock as "BASE_BAUD * 16". In case of ARC "BASE_BAUD" is calculated dynamically in runtime, basically it is an alias to arc_early_base_baud(), which in turn just does "arc_base_baud/16". 8250 UART on AXS/SDP board uses 33.3MHz clock source which is set in "arc_base_baud" with this change. Additional compatibility string "snps,arc-sdp" is introduced as well because there're different flavours of AXS boards but they all share the same motherboard and so it's possible to re-use the same code for motherbord even if CPU daughterboard changes. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
8 lines
306 B
Plaintext
8 lines
306 B
Plaintext
Synopsys DesignWare ARC Software Development Platforms Device Tree Bindings
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SDP Main Board with an AXC001 CPU Card hoisting ARC700 core in silicon
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Required root node properties:
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- compatible = "snps,axs101", "snps,arc-sdp";
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