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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5fd39c4d96
This patch adds support for the EIP196, which is an EIP197 derivative that has no classification hardware and a simplified record cache. The patch has been tested with the eip196b-ie and eip197c-iewxkbc configurations on the Xilinx VCU118 development board as well as on the Macchiatobin board (Marvell A8K - EIP197b-ieswx), including the crypto extra tests. Note that this patchset applies on top of the earlier submitted "Add support for eip197f_iewc" series. Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
190 lines
4.9 KiB
C
190 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Marvell
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*
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* Antoine Tenart <antoine.tenart@free-electrons.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/spinlock.h>
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#include "safexcel.h"
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int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *cdr,
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struct safexcel_desc_ring *rdr)
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{
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cdr->offset = priv->config.cd_offset;
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cdr->base = dmam_alloc_coherent(priv->dev,
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cdr->offset * EIP197_DEFAULT_RING_SIZE,
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&cdr->base_dma, GFP_KERNEL);
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if (!cdr->base)
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return -ENOMEM;
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cdr->write = cdr->base;
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cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
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cdr->read = cdr->base;
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rdr->offset = priv->config.rd_offset;
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rdr->base = dmam_alloc_coherent(priv->dev,
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rdr->offset * EIP197_DEFAULT_RING_SIZE,
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&rdr->base_dma, GFP_KERNEL);
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if (!rdr->base)
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return -ENOMEM;
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rdr->write = rdr->base;
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rdr->base_end = rdr->base + rdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
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rdr->read = rdr->base;
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return 0;
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}
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inline int safexcel_select_ring(struct safexcel_crypto_priv *priv)
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{
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return (atomic_inc_return(&priv->ring_used) % priv->config.rings);
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}
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static void *safexcel_ring_next_wptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring)
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{
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void *ptr = ring->write;
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if ((ring->write == ring->read - ring->offset) ||
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(ring->read == ring->base && ring->write == ring->base_end))
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return ERR_PTR(-ENOMEM);
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if (ring->write == ring->base_end)
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ring->write = ring->base;
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else
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ring->write += ring->offset;
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return ptr;
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}
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void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring)
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{
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void *ptr = ring->read;
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if (ring->write == ring->read)
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return ERR_PTR(-ENOENT);
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if (ring->read == ring->base_end)
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ring->read = ring->base;
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else
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ring->read += ring->offset;
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return ptr;
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}
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inline void *safexcel_ring_curr_rptr(struct safexcel_crypto_priv *priv,
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int ring)
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{
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struct safexcel_desc_ring *rdr = &priv->ring[ring].rdr;
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return rdr->read;
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}
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inline int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
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int ring)
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{
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struct safexcel_desc_ring *rdr = &priv->ring[ring].rdr;
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return (rdr->read - rdr->base) / rdr->offset;
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}
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inline int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
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int ring,
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struct safexcel_result_desc *rdesc)
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{
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struct safexcel_desc_ring *rdr = &priv->ring[ring].rdr;
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return ((void *)rdesc - rdr->base) / rdr->offset;
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}
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void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *ring)
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{
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if (ring->write == ring->read)
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return;
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if (ring->write == ring->base)
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ring->write = ring->base_end;
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else
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ring->write -= ring->offset;
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}
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struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
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int ring_id,
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bool first, bool last,
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dma_addr_t data, u32 data_len,
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u32 full_data_len,
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dma_addr_t context) {
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struct safexcel_command_desc *cdesc;
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int i;
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cdesc = safexcel_ring_next_wptr(priv, &priv->ring[ring_id].cdr);
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if (IS_ERR(cdesc))
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return cdesc;
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memset(cdesc, 0, sizeof(struct safexcel_command_desc));
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cdesc->first_seg = first;
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cdesc->last_seg = last;
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cdesc->particle_size = data_len;
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cdesc->data_lo = lower_32_bits(data);
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cdesc->data_hi = upper_32_bits(data);
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if (first && context) {
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struct safexcel_token *token =
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(struct safexcel_token *)cdesc->control_data.token;
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/*
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* Note that the length here MUST be >0 or else the EIP(1)97
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* may hang. Newer EIP197 firmware actually incorporates this
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* fix already, but that doesn't help the EIP97 and we may
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* also be running older firmware.
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*/
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cdesc->control_data.packet_length = full_data_len ?: 1;
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cdesc->control_data.options = EIP197_OPTION_MAGIC_VALUE |
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EIP197_OPTION_64BIT_CTX |
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EIP197_OPTION_CTX_CTRL_IN_CMD;
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cdesc->control_data.context_lo =
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(lower_32_bits(context) & GENMASK(31, 2)) >> 2;
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cdesc->control_data.context_hi = upper_32_bits(context);
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if (priv->version == EIP197B_MRVL ||
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priv->version == EIP197D_MRVL)
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cdesc->control_data.options |= EIP197_OPTION_RC_AUTO;
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/* TODO: large xform HMAC with SHA-384/512 uses refresh = 3 */
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cdesc->control_data.refresh = 2;
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for (i = 0; i < EIP197_MAX_TOKENS; i++)
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eip197_noop_token(&token[i]);
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}
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return cdesc;
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}
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struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
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int ring_id,
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bool first, bool last,
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dma_addr_t data, u32 len)
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{
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struct safexcel_result_desc *rdesc;
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rdesc = safexcel_ring_next_wptr(priv, &priv->ring[ring_id].rdr);
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if (IS_ERR(rdesc))
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return rdesc;
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memset(rdesc, 0, sizeof(struct safexcel_result_desc));
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rdesc->first_seg = first;
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rdesc->last_seg = last;
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rdesc->result_size = EIP197_RD64_RESULT_SIZE;
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rdesc->particle_size = len;
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rdesc->data_lo = lower_32_bits(data);
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rdesc->data_hi = upper_32_bits(data);
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return rdesc;
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}
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