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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6ed6bd84ea
Found by running the semicolon.cocci spatch: https://github.com/coccinelle/coccinellery/blob/master/semicolon/semicolon.cocci Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
518 lines
14 KiB
C
518 lines
14 KiB
C
/*
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*
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* Copyright (c) 2012 Gilles Dartiguelongue, Thomas Richter
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "dvo.h"
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#include "i915_reg.h"
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#include "i915_drv.h"
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#define NS2501_VID 0x1305
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#define NS2501_DID 0x6726
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#define NS2501_VID_LO 0x00
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#define NS2501_VID_HI 0x01
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#define NS2501_DID_LO 0x02
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#define NS2501_DID_HI 0x03
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#define NS2501_REV 0x04
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#define NS2501_RSVD 0x05
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#define NS2501_FREQ_LO 0x06
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#define NS2501_FREQ_HI 0x07
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#define NS2501_REG8 0x08
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#define NS2501_8_VEN (1<<5)
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#define NS2501_8_HEN (1<<4)
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#define NS2501_8_DSEL (1<<3)
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#define NS2501_8_BPAS (1<<2)
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#define NS2501_8_RSVD (1<<1)
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#define NS2501_8_PD (1<<0)
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#define NS2501_REG9 0x09
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#define NS2501_9_VLOW (1<<7)
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#define NS2501_9_MSEL_MASK (0x7<<4)
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#define NS2501_9_TSEL (1<<3)
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#define NS2501_9_RSEN (1<<2)
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#define NS2501_9_RSVD (1<<1)
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#define NS2501_9_MDI (1<<0)
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#define NS2501_REGC 0x0c
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struct ns2501_priv {
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//I2CDevRec d;
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bool quiet;
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int reg_8_shadow;
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int reg_8_set;
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// Shadow registers for i915
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int dvoc;
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int pll_a;
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int srcdim;
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int fw_blc;
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};
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#define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
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/*
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* For reasons unclear to me, the ns2501 at least on the Fujitsu/Siemens
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* laptops does not react on the i2c bus unless
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* both the PLL is running and the display is configured in its native
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* resolution.
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* This function forces the DVO on, and stores the registers it touches.
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* Afterwards, registers are restored to regular values.
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*
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* This is pretty much a hack, though it works.
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* Without that, ns2501_readb and ns2501_writeb fail
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* when switching the resolution.
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*/
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/*
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** Read a register from the ns2501.
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** Returns true if successful, false otherwise.
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** If it returns false, it might be wise to enable the
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** DVO with the above function.
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*/
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static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, uint8_t * ch)
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{
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struct ns2501_priv *ns = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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u8 out_buf[2];
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u8 in_buf[2];
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struct i2c_msg msgs[] = {
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{
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 1,
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.buf = out_buf,
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},
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{
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.addr = dvo->slave_addr,
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.flags = I2C_M_RD,
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.len = 1,
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.buf = in_buf,
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}
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};
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out_buf[0] = addr;
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out_buf[1] = 0;
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if (i2c_transfer(adapter, msgs, 2) == 2) {
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*ch = in_buf[0];
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return true;
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}
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if (!ns->quiet) {
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DRM_DEBUG_KMS
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("Unable to read register 0x%02x from %s:0x%02x.\n", addr,
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adapter->name, dvo->slave_addr);
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}
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return false;
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}
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/*
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** Write a register to the ns2501.
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** Returns true if successful, false otherwise.
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** If it returns false, it might be wise to enable the
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** DVO with the above function.
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*/
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static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
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{
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struct ns2501_priv *ns = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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uint8_t out_buf[2];
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struct i2c_msg msg = {
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 2,
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.buf = out_buf,
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};
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out_buf[0] = addr;
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out_buf[1] = ch;
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if (i2c_transfer(adapter, &msg, 1) == 1) {
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return true;
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}
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if (!ns->quiet) {
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DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d\n",
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addr, adapter->name, dvo->slave_addr);
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}
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return false;
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}
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/* National Semiconductor 2501 driver for chip on i2c bus
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* scan for the chip on the bus.
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* Hope the VBIOS initialized the PLL correctly so we can
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* talk to it. If not, it will not be seen and not detected.
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* Bummer!
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*/
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static bool ns2501_init(struct intel_dvo_device *dvo,
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struct i2c_adapter *adapter)
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{
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/* this will detect the NS2501 chip on the specified i2c bus */
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struct ns2501_priv *ns;
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unsigned char ch;
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ns = kzalloc(sizeof(struct ns2501_priv), GFP_KERNEL);
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if (ns == NULL)
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return false;
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dvo->i2c_bus = adapter;
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dvo->dev_priv = ns;
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ns->quiet = true;
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if (!ns2501_readb(dvo, NS2501_VID_LO, &ch))
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goto out;
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if (ch != (NS2501_VID & 0xff)) {
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DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n",
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ch, adapter->name, dvo->slave_addr);
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goto out;
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}
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if (!ns2501_readb(dvo, NS2501_DID_LO, &ch))
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goto out;
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if (ch != (NS2501_DID & 0xff)) {
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DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Slave %d.\n",
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ch, adapter->name, dvo->slave_addr);
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goto out;
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}
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ns->quiet = false;
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ns->reg_8_set = 0;
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ns->reg_8_shadow =
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NS2501_8_PD | NS2501_8_BPAS | NS2501_8_VEN | NS2501_8_HEN;
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DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n");
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return true;
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out:
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kfree(ns);
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return false;
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}
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static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo)
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{
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/*
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* This is a Laptop display, it doesn't have hotplugging.
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* Even if not, the detection bit of the 2501 is unreliable as
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* it only works for some display types.
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* It is even more unreliable as the PLL must be active for
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* allowing reading from the chiop.
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*/
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return connector_status_connected;
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}
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static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode)
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{
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DRM_DEBUG_KMS
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("is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)\n",
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mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
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/*
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* Currently, these are all the modes I have data from.
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* More might exist. Unclear how to find the native resolution
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* of the panel in here so we could always accept it
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* by disabling the scaler.
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*/
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if ((mode->hdisplay == 800 && mode->vdisplay == 600) ||
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(mode->hdisplay == 640 && mode->vdisplay == 480) ||
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(mode->hdisplay == 1024 && mode->vdisplay == 768)) {
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return MODE_OK;
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} else {
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return MODE_ONE_SIZE; /* Is this a reasonable error? */
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}
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}
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static void ns2501_mode_set(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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bool ok;
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int retries = 10;
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struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
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DRM_DEBUG_KMS
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("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n",
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mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
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/*
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* Where do I find the native resolution for which scaling is not required???
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*
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* First trigger the DVO on as otherwise the chip does not appear on the i2c
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* bus.
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*/
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do {
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ok = true;
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if (mode->hdisplay == 800 && mode->vdisplay == 600) {
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/* mode 277 */
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ns->reg_8_shadow &= ~NS2501_8_BPAS;
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DRM_DEBUG_KMS("switching to 800x600\n");
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/*
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* No, I do not know where this data comes from.
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* It is just what the video bios left in the DVO, so
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* I'm just copying it here over.
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* This also means that I cannot support any other modes
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* except the ones supported by the bios.
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*/
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ok &= ns2501_writeb(dvo, 0x11, 0xc8); // 0xc7 also works.
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ok &= ns2501_writeb(dvo, 0x1b, 0x19);
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ok &= ns2501_writeb(dvo, 0x1c, 0x62); // VBIOS left 0x64 here, but 0x62 works nicer
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ok &= ns2501_writeb(dvo, 0x1d, 0x02);
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ok &= ns2501_writeb(dvo, 0x34, 0x03);
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ok &= ns2501_writeb(dvo, 0x35, 0xff);
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ok &= ns2501_writeb(dvo, 0x80, 0x27);
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ok &= ns2501_writeb(dvo, 0x81, 0x03);
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ok &= ns2501_writeb(dvo, 0x82, 0x41);
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ok &= ns2501_writeb(dvo, 0x83, 0x05);
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ok &= ns2501_writeb(dvo, 0x8d, 0x02);
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ok &= ns2501_writeb(dvo, 0x8e, 0x04);
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ok &= ns2501_writeb(dvo, 0x8f, 0x00);
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ok &= ns2501_writeb(dvo, 0x90, 0xfe); /* vertical. VBIOS left 0xff here, but 0xfe works better */
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ok &= ns2501_writeb(dvo, 0x91, 0x07);
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ok &= ns2501_writeb(dvo, 0x94, 0x00);
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ok &= ns2501_writeb(dvo, 0x95, 0x00);
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ok &= ns2501_writeb(dvo, 0x96, 0x00);
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ok &= ns2501_writeb(dvo, 0x99, 0x00);
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ok &= ns2501_writeb(dvo, 0x9a, 0x88);
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ok &= ns2501_writeb(dvo, 0x9c, 0x23); /* Looks like first and last line of the image. */
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ok &= ns2501_writeb(dvo, 0x9d, 0x00);
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ok &= ns2501_writeb(dvo, 0x9e, 0x25);
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ok &= ns2501_writeb(dvo, 0x9f, 0x03);
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ok &= ns2501_writeb(dvo, 0xa4, 0x80);
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ok &= ns2501_writeb(dvo, 0xb6, 0x00);
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ok &= ns2501_writeb(dvo, 0xb9, 0xc8); /* horizontal? */
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ok &= ns2501_writeb(dvo, 0xba, 0x00); /* horizontal? */
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ok &= ns2501_writeb(dvo, 0xc0, 0x05); /* horizontal? */
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ok &= ns2501_writeb(dvo, 0xc1, 0xd7);
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ok &= ns2501_writeb(dvo, 0xc2, 0x00);
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ok &= ns2501_writeb(dvo, 0xc3, 0xf8);
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ok &= ns2501_writeb(dvo, 0xc4, 0x03);
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ok &= ns2501_writeb(dvo, 0xc5, 0x1a);
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ok &= ns2501_writeb(dvo, 0xc6, 0x00);
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ok &= ns2501_writeb(dvo, 0xc7, 0x73);
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ok &= ns2501_writeb(dvo, 0xc8, 0x02);
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} else if (mode->hdisplay == 640 && mode->vdisplay == 480) {
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/* mode 274 */
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DRM_DEBUG_KMS("switching to 640x480\n");
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/*
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* No, I do not know where this data comes from.
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* It is just what the video bios left in the DVO, so
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* I'm just copying it here over.
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* This also means that I cannot support any other modes
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* except the ones supported by the bios.
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*/
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ns->reg_8_shadow &= ~NS2501_8_BPAS;
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ok &= ns2501_writeb(dvo, 0x11, 0xa0);
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ok &= ns2501_writeb(dvo, 0x1b, 0x11);
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ok &= ns2501_writeb(dvo, 0x1c, 0x54);
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ok &= ns2501_writeb(dvo, 0x1d, 0x03);
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ok &= ns2501_writeb(dvo, 0x34, 0x03);
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ok &= ns2501_writeb(dvo, 0x35, 0xff);
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ok &= ns2501_writeb(dvo, 0x80, 0xff);
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ok &= ns2501_writeb(dvo, 0x81, 0x07);
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ok &= ns2501_writeb(dvo, 0x82, 0x3d);
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ok &= ns2501_writeb(dvo, 0x83, 0x05);
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ok &= ns2501_writeb(dvo, 0x8d, 0x02);
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ok &= ns2501_writeb(dvo, 0x8e, 0x10);
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ok &= ns2501_writeb(dvo, 0x8f, 0x00);
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ok &= ns2501_writeb(dvo, 0x90, 0xff); /* vertical */
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ok &= ns2501_writeb(dvo, 0x91, 0x07);
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ok &= ns2501_writeb(dvo, 0x94, 0x00);
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ok &= ns2501_writeb(dvo, 0x95, 0x00);
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ok &= ns2501_writeb(dvo, 0x96, 0x05);
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ok &= ns2501_writeb(dvo, 0x99, 0x00);
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ok &= ns2501_writeb(dvo, 0x9a, 0x88);
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ok &= ns2501_writeb(dvo, 0x9c, 0x24);
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ok &= ns2501_writeb(dvo, 0x9d, 0x00);
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ok &= ns2501_writeb(dvo, 0x9e, 0x25);
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ok &= ns2501_writeb(dvo, 0x9f, 0x03);
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ok &= ns2501_writeb(dvo, 0xa4, 0x84);
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ok &= ns2501_writeb(dvo, 0xb6, 0x09);
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ok &= ns2501_writeb(dvo, 0xb9, 0xa0); /* horizontal? */
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ok &= ns2501_writeb(dvo, 0xba, 0x00); /* horizontal? */
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ok &= ns2501_writeb(dvo, 0xc0, 0x05); /* horizontal? */
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ok &= ns2501_writeb(dvo, 0xc1, 0x90);
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ok &= ns2501_writeb(dvo, 0xc2, 0x00);
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ok &= ns2501_writeb(dvo, 0xc3, 0x0f);
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ok &= ns2501_writeb(dvo, 0xc4, 0x03);
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ok &= ns2501_writeb(dvo, 0xc5, 0x16);
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ok &= ns2501_writeb(dvo, 0xc6, 0x00);
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ok &= ns2501_writeb(dvo, 0xc7, 0x02);
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ok &= ns2501_writeb(dvo, 0xc8, 0x02);
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} else if (mode->hdisplay == 1024 && mode->vdisplay == 768) {
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/* mode 280 */
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DRM_DEBUG_KMS("switching to 1024x768\n");
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/*
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* This might or might not work, actually. I'm silently
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* assuming here that the native panel resolution is
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* 1024x768. If not, then this leaves the scaler disabled
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* generating a picture that is likely not the expected.
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*
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* Problem is that I do not know where to take the panel
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* dimensions from.
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*
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* Enable the bypass, scaling not required.
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*
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* The scaler registers are irrelevant here....
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*
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*/
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ns->reg_8_shadow |= NS2501_8_BPAS;
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ok &= ns2501_writeb(dvo, 0x37, 0x44);
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} else {
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/*
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* Data not known. Bummer!
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* Hopefully, the code should not go here
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* as mode_OK delivered no other modes.
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*/
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ns->reg_8_shadow |= NS2501_8_BPAS;
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}
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ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow);
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} while (!ok && retries--);
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}
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/* set the NS2501 power state */
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static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
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{
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unsigned char ch;
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if (!ns2501_readb(dvo, NS2501_REG8, &ch))
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return false;
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if (ch & NS2501_8_PD)
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return true;
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else
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return false;
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}
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/* set the NS2501 power state */
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static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
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{
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bool ok;
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int retries = 10;
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struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
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unsigned char ch;
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|
DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
|
|
|
|
ch = ns->reg_8_shadow;
|
|
|
|
if (enable)
|
|
ch |= NS2501_8_PD;
|
|
else
|
|
ch &= ~NS2501_8_PD;
|
|
|
|
if (ns->reg_8_set == 0 || ns->reg_8_shadow != ch) {
|
|
ns->reg_8_set = 1;
|
|
ns->reg_8_shadow = ch;
|
|
|
|
do {
|
|
ok = true;
|
|
ok &= ns2501_writeb(dvo, NS2501_REG8, ch);
|
|
ok &=
|
|
ns2501_writeb(dvo, 0x34,
|
|
enable ? 0x03 : 0x00);
|
|
ok &=
|
|
ns2501_writeb(dvo, 0x35,
|
|
enable ? 0xff : 0x00);
|
|
} while (!ok && retries--);
|
|
}
|
|
}
|
|
|
|
static void ns2501_dump_regs(struct intel_dvo_device *dvo)
|
|
{
|
|
uint8_t val;
|
|
|
|
ns2501_readb(dvo, NS2501_FREQ_LO, &val);
|
|
DRM_DEBUG_KMS("NS2501_FREQ_LO: 0x%02x\n", val);
|
|
ns2501_readb(dvo, NS2501_FREQ_HI, &val);
|
|
DRM_DEBUG_KMS("NS2501_FREQ_HI: 0x%02x\n", val);
|
|
ns2501_readb(dvo, NS2501_REG8, &val);
|
|
DRM_DEBUG_KMS("NS2501_REG8: 0x%02x\n", val);
|
|
ns2501_readb(dvo, NS2501_REG9, &val);
|
|
DRM_DEBUG_KMS("NS2501_REG9: 0x%02x\n", val);
|
|
ns2501_readb(dvo, NS2501_REGC, &val);
|
|
DRM_DEBUG_KMS("NS2501_REGC: 0x%02x\n", val);
|
|
}
|
|
|
|
static void ns2501_destroy(struct intel_dvo_device *dvo)
|
|
{
|
|
struct ns2501_priv *ns = dvo->dev_priv;
|
|
|
|
if (ns) {
|
|
kfree(ns);
|
|
dvo->dev_priv = NULL;
|
|
}
|
|
}
|
|
|
|
struct intel_dvo_dev_ops ns2501_ops = {
|
|
.init = ns2501_init,
|
|
.detect = ns2501_detect,
|
|
.mode_valid = ns2501_mode_valid,
|
|
.mode_set = ns2501_mode_set,
|
|
.dpms = ns2501_dpms,
|
|
.get_hw_state = ns2501_get_hw_state,
|
|
.dump_regs = ns2501_dump_regs,
|
|
.destroy = ns2501_destroy,
|
|
};
|