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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cd7e61b93d
There is one issue relates to Coarse Power Gating(CPG) on KBL NUC in GVT-g, vgpu can't get the correct default context by updating the registers before inhibit context submission. It always get back the hardware default value unless the inhibit context submission happened before the 1st time forcewake put. With this wrong default context, vgpu will run with incorrect state and meet unknown issues. The solution is initialize these mmios by adding lri command in ring buffer of the inhibit context, then gpu hardware has no chance to go down RC6 when lri commands are right being executed, and then vgpu can get correct default context for further use. v3: - fix code fault, use 'for' to loop through mmio render list(Zhenyu) v4: - save the count of engine mmio need to be restored for inhibit context and refine some comments. (Kevin) v5: - code rebase Cc: Kevin Tian <kevin.tian@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Weinan Li <weinan.z.li@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Eddie Dong <eddie.dong@intel.com>
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* Kevin Tian <kevin.tian@intel.com>
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*
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* Contributors:
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* Zhi Wang <zhi.a.wang@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Bing Niu <bing.niu@intel.com>
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*
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*/
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#ifndef __GVT_RENDER_H__
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#define __GVT_RENDER_H__
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struct engine_mmio {
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int ring_id;
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i915_reg_t reg;
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u32 mask;
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bool in_context;
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u32 value;
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};
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void intel_gvt_switch_mmio(struct intel_vgpu *pre,
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struct intel_vgpu *next, int ring_id);
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void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt);
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bool is_inhibit_context(struct i915_gem_context *ctx, int ring_id);
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int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
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struct i915_request *req);
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#endif
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