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3dcc1e7f9f
Split the PLL control code from the Blackfin machine-specific cdef headers so that the irqflags functions can be renamed without incurring a header loop. Signed-off-by: David Howells <dhowells@redhat.com>
58 lines
1.1 KiB
C
58 lines
1.1 KiB
C
/*
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* Copyright 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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#endif /* _MACH_PLL_H */
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