mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:26:42 +07:00
0fa035e523
The flush_iotlb_page is not loading the cam register before flushing the cam entry. This causes wrong entry to be flushed out from the TLB, and if the entry happens to be a locked TLB entry it would lead to MMU faults. The fix is to load the cam register with the address to be flushed before flushing the TLB entry. Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Acked-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
1050 lines
22 KiB
C
1050 lines
22 KiB
C
/*
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* omap iommu: tlb and pagetable primitives
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*
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* Copyright (C) 2008-2010 Nokia Corporation
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*
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* Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
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* Paul Mundt and Toshihiro Kobayashi
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <asm/cacheflush.h>
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#include <plat/iommu.h>
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#include "iopgtable.h"
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#define for_each_iotlb_cr(obj, n, __i, cr) \
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for (__i = 0; \
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(__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
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__i++)
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/* accommodate the difference between omap1 and omap2/3 */
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static const struct iommu_functions *arch_iommu;
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static struct platform_driver omap_iommu_driver;
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static struct kmem_cache *iopte_cachep;
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/**
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* install_iommu_arch - Install archtecure specific iommu functions
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* @ops: a pointer to architecture specific iommu functions
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*
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* There are several kind of iommu algorithm(tlb, pagetable) among
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* omap series. This interface installs such an iommu algorighm.
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**/
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int install_iommu_arch(const struct iommu_functions *ops)
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{
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if (arch_iommu)
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return -EBUSY;
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arch_iommu = ops;
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return 0;
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}
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EXPORT_SYMBOL_GPL(install_iommu_arch);
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/**
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* uninstall_iommu_arch - Uninstall archtecure specific iommu functions
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* @ops: a pointer to architecture specific iommu functions
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*
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* This interface uninstalls the iommu algorighm installed previously.
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**/
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void uninstall_iommu_arch(const struct iommu_functions *ops)
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{
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if (arch_iommu != ops)
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pr_err("%s: not your arch\n", __func__);
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arch_iommu = NULL;
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}
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EXPORT_SYMBOL_GPL(uninstall_iommu_arch);
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/**
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* iommu_save_ctx - Save registers for pm off-mode support
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* @obj: target iommu
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**/
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void iommu_save_ctx(struct iommu *obj)
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{
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arch_iommu->save_ctx(obj);
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}
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EXPORT_SYMBOL_GPL(iommu_save_ctx);
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/**
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* iommu_restore_ctx - Restore registers for pm off-mode support
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* @obj: target iommu
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**/
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void iommu_restore_ctx(struct iommu *obj)
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{
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arch_iommu->restore_ctx(obj);
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}
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EXPORT_SYMBOL_GPL(iommu_restore_ctx);
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/**
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* iommu_arch_version - Return running iommu arch version
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**/
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u32 iommu_arch_version(void)
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{
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return arch_iommu->version;
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}
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EXPORT_SYMBOL_GPL(iommu_arch_version);
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static int iommu_enable(struct iommu *obj)
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{
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int err;
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if (!obj)
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return -EINVAL;
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clk_enable(obj->clk);
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err = arch_iommu->enable(obj);
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clk_disable(obj->clk);
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return err;
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}
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static void iommu_disable(struct iommu *obj)
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{
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if (!obj)
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return;
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clk_enable(obj->clk);
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arch_iommu->disable(obj);
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clk_disable(obj->clk);
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}
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/*
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* TLB operations
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*/
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void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
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{
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BUG_ON(!cr || !e);
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arch_iommu->cr_to_e(cr, e);
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}
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EXPORT_SYMBOL_GPL(iotlb_cr_to_e);
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static inline int iotlb_cr_valid(struct cr_regs *cr)
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{
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if (!cr)
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return -EINVAL;
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return arch_iommu->cr_valid(cr);
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}
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static inline struct cr_regs *iotlb_alloc_cr(struct iommu *obj,
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struct iotlb_entry *e)
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{
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if (!e)
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return NULL;
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return arch_iommu->alloc_cr(obj, e);
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}
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u32 iotlb_cr_to_virt(struct cr_regs *cr)
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{
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return arch_iommu->cr_to_virt(cr);
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}
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EXPORT_SYMBOL_GPL(iotlb_cr_to_virt);
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static u32 get_iopte_attr(struct iotlb_entry *e)
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{
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return arch_iommu->get_pte_attr(e);
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}
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static u32 iommu_report_fault(struct iommu *obj, u32 *da)
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{
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return arch_iommu->fault_isr(obj, da);
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}
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static void iotlb_lock_get(struct iommu *obj, struct iotlb_lock *l)
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{
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u32 val;
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val = iommu_read_reg(obj, MMU_LOCK);
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l->base = MMU_LOCK_BASE(val);
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l->vict = MMU_LOCK_VICT(val);
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}
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static void iotlb_lock_set(struct iommu *obj, struct iotlb_lock *l)
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{
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u32 val;
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val = (l->base << MMU_LOCK_BASE_SHIFT);
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val |= (l->vict << MMU_LOCK_VICT_SHIFT);
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iommu_write_reg(obj, val, MMU_LOCK);
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}
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static void iotlb_read_cr(struct iommu *obj, struct cr_regs *cr)
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{
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arch_iommu->tlb_read_cr(obj, cr);
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}
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static void iotlb_load_cr(struct iommu *obj, struct cr_regs *cr)
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{
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arch_iommu->tlb_load_cr(obj, cr);
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iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
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iommu_write_reg(obj, 1, MMU_LD_TLB);
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}
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/**
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* iotlb_dump_cr - Dump an iommu tlb entry into buf
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* @obj: target iommu
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* @cr: contents of cam and ram register
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* @buf: output buffer
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**/
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static inline ssize_t iotlb_dump_cr(struct iommu *obj, struct cr_regs *cr,
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char *buf)
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{
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BUG_ON(!cr || !buf);
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return arch_iommu->dump_cr(obj, cr, buf);
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}
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/* only used in iotlb iteration for-loop */
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static struct cr_regs __iotlb_read_cr(struct iommu *obj, int n)
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{
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struct cr_regs cr;
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struct iotlb_lock l;
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iotlb_lock_get(obj, &l);
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l.vict = n;
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iotlb_lock_set(obj, &l);
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iotlb_read_cr(obj, &cr);
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return cr;
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}
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/**
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* load_iotlb_entry - Set an iommu tlb entry
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* @obj: target iommu
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* @e: an iommu tlb entry info
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**/
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int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e)
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{
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int err = 0;
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struct iotlb_lock l;
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struct cr_regs *cr;
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if (!obj || !obj->nr_tlb_entries || !e)
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return -EINVAL;
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clk_enable(obj->clk);
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iotlb_lock_get(obj, &l);
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if (l.base == obj->nr_tlb_entries) {
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dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
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err = -EBUSY;
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goto out;
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}
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if (!e->prsvd) {
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int i;
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struct cr_regs tmp;
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for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
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if (!iotlb_cr_valid(&tmp))
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break;
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if (i == obj->nr_tlb_entries) {
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dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
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err = -EBUSY;
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goto out;
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}
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iotlb_lock_get(obj, &l);
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} else {
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l.vict = l.base;
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iotlb_lock_set(obj, &l);
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}
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cr = iotlb_alloc_cr(obj, e);
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if (IS_ERR(cr)) {
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clk_disable(obj->clk);
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return PTR_ERR(cr);
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}
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iotlb_load_cr(obj, cr);
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kfree(cr);
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if (e->prsvd)
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l.base++;
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/* increment victim for next tlb load */
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if (++l.vict == obj->nr_tlb_entries)
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l.vict = l.base;
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iotlb_lock_set(obj, &l);
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out:
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clk_disable(obj->clk);
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return err;
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}
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EXPORT_SYMBOL_GPL(load_iotlb_entry);
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/**
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* flush_iotlb_page - Clear an iommu tlb entry
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* @obj: target iommu
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* @da: iommu device virtual address
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*
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* Clear an iommu tlb entry which includes 'da' address.
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**/
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void flush_iotlb_page(struct iommu *obj, u32 da)
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{
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int i;
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struct cr_regs cr;
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clk_enable(obj->clk);
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for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
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u32 start;
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size_t bytes;
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if (!iotlb_cr_valid(&cr))
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continue;
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start = iotlb_cr_to_virt(&cr);
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bytes = iopgsz_to_bytes(cr.cam & 3);
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if ((start <= da) && (da < start + bytes)) {
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dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
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__func__, start, da, bytes);
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iotlb_load_cr(obj, &cr);
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iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
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}
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}
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clk_disable(obj->clk);
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if (i == obj->nr_tlb_entries)
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dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
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}
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EXPORT_SYMBOL_GPL(flush_iotlb_page);
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/**
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* flush_iotlb_range - Clear an iommu tlb entries
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* @obj: target iommu
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* @start: iommu device virtual address(start)
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* @end: iommu device virtual address(end)
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*
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* Clear an iommu tlb entry which includes 'da' address.
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**/
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void flush_iotlb_range(struct iommu *obj, u32 start, u32 end)
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{
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u32 da = start;
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while (da < end) {
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flush_iotlb_page(obj, da);
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/* FIXME: Optimize for multiple page size */
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da += IOPTE_SIZE;
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}
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}
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EXPORT_SYMBOL_GPL(flush_iotlb_range);
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/**
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* flush_iotlb_all - Clear all iommu tlb entries
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* @obj: target iommu
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**/
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void flush_iotlb_all(struct iommu *obj)
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{
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struct iotlb_lock l;
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clk_enable(obj->clk);
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l.base = 0;
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l.vict = 0;
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iotlb_lock_set(obj, &l);
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iommu_write_reg(obj, 1, MMU_GFLUSH);
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clk_disable(obj->clk);
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}
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EXPORT_SYMBOL_GPL(flush_iotlb_all);
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/**
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* iommu_set_twl - enable/disable table walking logic
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* @obj: target iommu
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* @on: enable/disable
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*
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* Function used to enable/disable TWL. If one wants to work
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* exclusively with locked TLB entries and receive notifications
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* for TLB miss then call this function to disable TWL.
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*/
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void iommu_set_twl(struct iommu *obj, bool on)
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{
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clk_enable(obj->clk);
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arch_iommu->set_twl(obj, on);
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clk_disable(obj->clk);
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}
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EXPORT_SYMBOL_GPL(iommu_set_twl);
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#if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
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ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
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{
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if (!obj || !buf)
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return -EINVAL;
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clk_enable(obj->clk);
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bytes = arch_iommu->dump_ctx(obj, buf, bytes);
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clk_disable(obj->clk);
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return bytes;
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}
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EXPORT_SYMBOL_GPL(iommu_dump_ctx);
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static int __dump_tlb_entries(struct iommu *obj, struct cr_regs *crs, int num)
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{
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int i;
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struct iotlb_lock saved;
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struct cr_regs tmp;
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struct cr_regs *p = crs;
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clk_enable(obj->clk);
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iotlb_lock_get(obj, &saved);
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for_each_iotlb_cr(obj, num, i, tmp) {
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if (!iotlb_cr_valid(&tmp))
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continue;
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*p++ = tmp;
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}
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iotlb_lock_set(obj, &saved);
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clk_disable(obj->clk);
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return p - crs;
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}
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/**
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* dump_tlb_entries - dump cr arrays to given buffer
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* @obj: target iommu
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* @buf: output buffer
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**/
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size_t dump_tlb_entries(struct iommu *obj, char *buf, ssize_t bytes)
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{
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int i, num;
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struct cr_regs *cr;
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char *p = buf;
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num = bytes / sizeof(*cr);
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num = min(obj->nr_tlb_entries, num);
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cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
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if (!cr)
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return 0;
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num = __dump_tlb_entries(obj, cr, num);
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for (i = 0; i < num; i++)
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p += iotlb_dump_cr(obj, cr + i, p);
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kfree(cr);
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return p - buf;
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}
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EXPORT_SYMBOL_GPL(dump_tlb_entries);
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int foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
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{
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return driver_for_each_device(&omap_iommu_driver.driver,
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NULL, data, fn);
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}
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EXPORT_SYMBOL_GPL(foreach_iommu_device);
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#endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
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/*
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* H/W pagetable operations
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*/
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static void flush_iopgd_range(u32 *first, u32 *last)
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{
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/* FIXME: L2 cache should be taken care of if it exists */
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do {
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asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
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: : "r" (first));
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first += L1_CACHE_BYTES / sizeof(*first);
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} while (first <= last);
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}
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static void flush_iopte_range(u32 *first, u32 *last)
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{
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/* FIXME: L2 cache should be taken care of if it exists */
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do {
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asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
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: : "r" (first));
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first += L1_CACHE_BYTES / sizeof(*first);
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} while (first <= last);
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}
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static void iopte_free(u32 *iopte)
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{
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/* Note: freed iopte's must be clean ready for re-use */
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kmem_cache_free(iopte_cachep, iopte);
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}
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static u32 *iopte_alloc(struct iommu *obj, u32 *iopgd, u32 da)
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{
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u32 *iopte;
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/* a table has already existed */
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if (*iopgd)
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goto pte_ready;
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/*
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* do the allocation outside the page table lock
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*/
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spin_unlock(&obj->page_table_lock);
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iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
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spin_lock(&obj->page_table_lock);
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if (!*iopgd) {
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if (!iopte)
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return ERR_PTR(-ENOMEM);
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|
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*iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
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flush_iopgd_range(iopgd, iopgd);
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dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
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} else {
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/* We raced, free the reduniovant table */
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iopte_free(iopte);
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}
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pte_ready:
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iopte = iopte_offset(iopgd, da);
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|
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dev_vdbg(obj->dev,
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"%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
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__func__, da, iopgd, *iopgd, iopte, *iopte);
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return iopte;
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}
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|
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static int iopgd_alloc_section(struct iommu *obj, u32 da, u32 pa, u32 prot)
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{
|
|
u32 *iopgd = iopgd_offset(obj, da);
|
|
|
|
if ((da | pa) & ~IOSECTION_MASK) {
|
|
dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
|
|
__func__, da, pa, IOSECTION_SIZE);
|
|
return -EINVAL;
|
|
}
|
|
|
|
*iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
|
|
flush_iopgd_range(iopgd, iopgd);
|
|
return 0;
|
|
}
|
|
|
|
static int iopgd_alloc_super(struct iommu *obj, u32 da, u32 pa, u32 prot)
|
|
{
|
|
u32 *iopgd = iopgd_offset(obj, da);
|
|
int i;
|
|
|
|
if ((da | pa) & ~IOSUPER_MASK) {
|
|
dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
|
|
__func__, da, pa, IOSUPER_SIZE);
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < 16; i++)
|
|
*(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
|
|
flush_iopgd_range(iopgd, iopgd + 15);
|
|
return 0;
|
|
}
|
|
|
|
static int iopte_alloc_page(struct iommu *obj, u32 da, u32 pa, u32 prot)
|
|
{
|
|
u32 *iopgd = iopgd_offset(obj, da);
|
|
u32 *iopte = iopte_alloc(obj, iopgd, da);
|
|
|
|
if (IS_ERR(iopte))
|
|
return PTR_ERR(iopte);
|
|
|
|
*iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
|
|
flush_iopte_range(iopte, iopte);
|
|
|
|
dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
|
|
__func__, da, pa, iopte, *iopte);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int iopte_alloc_large(struct iommu *obj, u32 da, u32 pa, u32 prot)
|
|
{
|
|
u32 *iopgd = iopgd_offset(obj, da);
|
|
u32 *iopte = iopte_alloc(obj, iopgd, da);
|
|
int i;
|
|
|
|
if ((da | pa) & ~IOLARGE_MASK) {
|
|
dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
|
|
__func__, da, pa, IOLARGE_SIZE);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (IS_ERR(iopte))
|
|
return PTR_ERR(iopte);
|
|
|
|
for (i = 0; i < 16; i++)
|
|
*(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
|
|
flush_iopte_range(iopte, iopte + 15);
|
|
return 0;
|
|
}
|
|
|
|
static int iopgtable_store_entry_core(struct iommu *obj, struct iotlb_entry *e)
|
|
{
|
|
int (*fn)(struct iommu *, u32, u32, u32);
|
|
u32 prot;
|
|
int err;
|
|
|
|
if (!obj || !e)
|
|
return -EINVAL;
|
|
|
|
switch (e->pgsz) {
|
|
case MMU_CAM_PGSZ_16M:
|
|
fn = iopgd_alloc_super;
|
|
break;
|
|
case MMU_CAM_PGSZ_1M:
|
|
fn = iopgd_alloc_section;
|
|
break;
|
|
case MMU_CAM_PGSZ_64K:
|
|
fn = iopte_alloc_large;
|
|
break;
|
|
case MMU_CAM_PGSZ_4K:
|
|
fn = iopte_alloc_page;
|
|
break;
|
|
default:
|
|
fn = NULL;
|
|
BUG();
|
|
break;
|
|
}
|
|
|
|
prot = get_iopte_attr(e);
|
|
|
|
spin_lock(&obj->page_table_lock);
|
|
err = fn(obj, e->da, e->pa, prot);
|
|
spin_unlock(&obj->page_table_lock);
|
|
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* iopgtable_store_entry - Make an iommu pte entry
|
|
* @obj: target iommu
|
|
* @e: an iommu tlb entry info
|
|
**/
|
|
int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e)
|
|
{
|
|
int err;
|
|
|
|
flush_iotlb_page(obj, e->da);
|
|
err = iopgtable_store_entry_core(obj, e);
|
|
#ifdef PREFETCH_IOTLB
|
|
if (!err)
|
|
load_iotlb_entry(obj, e);
|
|
#endif
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iopgtable_store_entry);
|
|
|
|
/**
|
|
* iopgtable_lookup_entry - Lookup an iommu pte entry
|
|
* @obj: target iommu
|
|
* @da: iommu device virtual address
|
|
* @ppgd: iommu pgd entry pointer to be returned
|
|
* @ppte: iommu pte entry pointer to be returned
|
|
**/
|
|
void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
|
|
{
|
|
u32 *iopgd, *iopte = NULL;
|
|
|
|
iopgd = iopgd_offset(obj, da);
|
|
if (!*iopgd)
|
|
goto out;
|
|
|
|
if (iopgd_is_table(*iopgd))
|
|
iopte = iopte_offset(iopgd, da);
|
|
out:
|
|
*ppgd = iopgd;
|
|
*ppte = iopte;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iopgtable_lookup_entry);
|
|
|
|
static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
|
|
{
|
|
size_t bytes;
|
|
u32 *iopgd = iopgd_offset(obj, da);
|
|
int nent = 1;
|
|
|
|
if (!*iopgd)
|
|
return 0;
|
|
|
|
if (iopgd_is_table(*iopgd)) {
|
|
int i;
|
|
u32 *iopte = iopte_offset(iopgd, da);
|
|
|
|
bytes = IOPTE_SIZE;
|
|
if (*iopte & IOPTE_LARGE) {
|
|
nent *= 16;
|
|
/* rewind to the 1st entry */
|
|
iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
|
|
}
|
|
bytes *= nent;
|
|
memset(iopte, 0, nent * sizeof(*iopte));
|
|
flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
|
|
|
|
/*
|
|
* do table walk to check if this table is necessary or not
|
|
*/
|
|
iopte = iopte_offset(iopgd, 0);
|
|
for (i = 0; i < PTRS_PER_IOPTE; i++)
|
|
if (iopte[i])
|
|
goto out;
|
|
|
|
iopte_free(iopte);
|
|
nent = 1; /* for the next L1 entry */
|
|
} else {
|
|
bytes = IOPGD_SIZE;
|
|
if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
|
|
nent *= 16;
|
|
/* rewind to the 1st entry */
|
|
iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
|
|
}
|
|
bytes *= nent;
|
|
}
|
|
memset(iopgd, 0, nent * sizeof(*iopgd));
|
|
flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
|
|
out:
|
|
return bytes;
|
|
}
|
|
|
|
/**
|
|
* iopgtable_clear_entry - Remove an iommu pte entry
|
|
* @obj: target iommu
|
|
* @da: iommu device virtual address
|
|
**/
|
|
size_t iopgtable_clear_entry(struct iommu *obj, u32 da)
|
|
{
|
|
size_t bytes;
|
|
|
|
spin_lock(&obj->page_table_lock);
|
|
|
|
bytes = iopgtable_clear_entry_core(obj, da);
|
|
flush_iotlb_page(obj, da);
|
|
|
|
spin_unlock(&obj->page_table_lock);
|
|
|
|
return bytes;
|
|
}
|
|
EXPORT_SYMBOL_GPL(iopgtable_clear_entry);
|
|
|
|
static void iopgtable_clear_entry_all(struct iommu *obj)
|
|
{
|
|
int i;
|
|
|
|
spin_lock(&obj->page_table_lock);
|
|
|
|
for (i = 0; i < PTRS_PER_IOPGD; i++) {
|
|
u32 da;
|
|
u32 *iopgd;
|
|
|
|
da = i << IOPGD_SHIFT;
|
|
iopgd = iopgd_offset(obj, da);
|
|
|
|
if (!*iopgd)
|
|
continue;
|
|
|
|
if (iopgd_is_table(*iopgd))
|
|
iopte_free(iopte_offset(iopgd, 0));
|
|
|
|
*iopgd = 0;
|
|
flush_iopgd_range(iopgd, iopgd);
|
|
}
|
|
|
|
flush_iotlb_all(obj);
|
|
|
|
spin_unlock(&obj->page_table_lock);
|
|
}
|
|
|
|
/*
|
|
* Device IOMMU generic operations
|
|
*/
|
|
static irqreturn_t iommu_fault_handler(int irq, void *data)
|
|
{
|
|
u32 stat, da;
|
|
u32 *iopgd, *iopte;
|
|
int err = -EIO;
|
|
struct iommu *obj = data;
|
|
|
|
if (!obj->refcount)
|
|
return IRQ_NONE;
|
|
|
|
/* Dynamic loading TLB or PTE */
|
|
if (obj->isr)
|
|
err = obj->isr(obj);
|
|
|
|
if (!err)
|
|
return IRQ_HANDLED;
|
|
|
|
clk_enable(obj->clk);
|
|
stat = iommu_report_fault(obj, &da);
|
|
clk_disable(obj->clk);
|
|
if (!stat)
|
|
return IRQ_HANDLED;
|
|
|
|
iommu_disable(obj);
|
|
|
|
iopgd = iopgd_offset(obj, da);
|
|
|
|
if (!iopgd_is_table(*iopgd)) {
|
|
dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
|
|
da, iopgd, *iopgd);
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
iopte = iopte_offset(iopgd, da);
|
|
|
|
dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
|
|
__func__, da, iopgd, *iopgd, iopte, *iopte);
|
|
|
|
return IRQ_NONE;
|
|
}
|
|
|
|
static int device_match_by_alias(struct device *dev, void *data)
|
|
{
|
|
struct iommu *obj = to_iommu(dev);
|
|
const char *name = data;
|
|
|
|
pr_debug("%s: %s %s\n", __func__, obj->name, name);
|
|
|
|
return strcmp(obj->name, name) == 0;
|
|
}
|
|
|
|
/**
|
|
* iommu_get - Get iommu handler
|
|
* @name: target iommu name
|
|
**/
|
|
struct iommu *iommu_get(const char *name)
|
|
{
|
|
int err = -ENOMEM;
|
|
struct device *dev;
|
|
struct iommu *obj;
|
|
|
|
dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
|
|
device_match_by_alias);
|
|
if (!dev)
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
obj = to_iommu(dev);
|
|
|
|
mutex_lock(&obj->iommu_lock);
|
|
|
|
if (obj->refcount++ == 0) {
|
|
err = iommu_enable(obj);
|
|
if (err)
|
|
goto err_enable;
|
|
flush_iotlb_all(obj);
|
|
}
|
|
|
|
if (!try_module_get(obj->owner))
|
|
goto err_module;
|
|
|
|
mutex_unlock(&obj->iommu_lock);
|
|
|
|
dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
|
|
return obj;
|
|
|
|
err_module:
|
|
if (obj->refcount == 1)
|
|
iommu_disable(obj);
|
|
err_enable:
|
|
obj->refcount--;
|
|
mutex_unlock(&obj->iommu_lock);
|
|
return ERR_PTR(err);
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_get);
|
|
|
|
/**
|
|
* iommu_put - Put back iommu handler
|
|
* @obj: target iommu
|
|
**/
|
|
void iommu_put(struct iommu *obj)
|
|
{
|
|
if (!obj || IS_ERR(obj))
|
|
return;
|
|
|
|
mutex_lock(&obj->iommu_lock);
|
|
|
|
if (--obj->refcount == 0)
|
|
iommu_disable(obj);
|
|
|
|
module_put(obj->owner);
|
|
|
|
mutex_unlock(&obj->iommu_lock);
|
|
|
|
dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
|
|
}
|
|
EXPORT_SYMBOL_GPL(iommu_put);
|
|
|
|
/*
|
|
* OMAP Device MMU(IOMMU) detection
|
|
*/
|
|
static int __devinit omap_iommu_probe(struct platform_device *pdev)
|
|
{
|
|
int err = -ENODEV;
|
|
void *p;
|
|
int irq;
|
|
struct iommu *obj;
|
|
struct resource *res;
|
|
struct iommu_platform_data *pdata = pdev->dev.platform_data;
|
|
|
|
if (pdev->num_resources != 2)
|
|
return -EINVAL;
|
|
|
|
obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
|
|
if (!obj)
|
|
return -ENOMEM;
|
|
|
|
obj->clk = clk_get(&pdev->dev, pdata->clk_name);
|
|
if (IS_ERR(obj->clk))
|
|
goto err_clk;
|
|
|
|
obj->nr_tlb_entries = pdata->nr_tlb_entries;
|
|
obj->name = pdata->name;
|
|
obj->dev = &pdev->dev;
|
|
obj->ctx = (void *)obj + sizeof(*obj);
|
|
|
|
mutex_init(&obj->iommu_lock);
|
|
mutex_init(&obj->mmap_lock);
|
|
spin_lock_init(&obj->page_table_lock);
|
|
INIT_LIST_HEAD(&obj->mmap);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
err = -ENODEV;
|
|
goto err_mem;
|
|
}
|
|
obj->regbase = ioremap(res->start, resource_size(res));
|
|
if (!obj->regbase) {
|
|
err = -ENOMEM;
|
|
goto err_mem;
|
|
}
|
|
|
|
res = request_mem_region(res->start, resource_size(res),
|
|
dev_name(&pdev->dev));
|
|
if (!res) {
|
|
err = -EIO;
|
|
goto err_mem;
|
|
}
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
err = -ENODEV;
|
|
goto err_irq;
|
|
}
|
|
err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
|
|
dev_name(&pdev->dev), obj);
|
|
if (err < 0)
|
|
goto err_irq;
|
|
platform_set_drvdata(pdev, obj);
|
|
|
|
p = (void *)__get_free_pages(GFP_KERNEL, get_order(IOPGD_TABLE_SIZE));
|
|
if (!p) {
|
|
err = -ENOMEM;
|
|
goto err_pgd;
|
|
}
|
|
memset(p, 0, IOPGD_TABLE_SIZE);
|
|
clean_dcache_area(p, IOPGD_TABLE_SIZE);
|
|
obj->iopgd = p;
|
|
|
|
BUG_ON(!IS_ALIGNED((unsigned long)obj->iopgd, IOPGD_TABLE_SIZE));
|
|
|
|
dev_info(&pdev->dev, "%s registered\n", obj->name);
|
|
return 0;
|
|
|
|
err_pgd:
|
|
free_irq(irq, obj);
|
|
err_irq:
|
|
release_mem_region(res->start, resource_size(res));
|
|
iounmap(obj->regbase);
|
|
err_mem:
|
|
clk_put(obj->clk);
|
|
err_clk:
|
|
kfree(obj);
|
|
return err;
|
|
}
|
|
|
|
static int __devexit omap_iommu_remove(struct platform_device *pdev)
|
|
{
|
|
int irq;
|
|
struct resource *res;
|
|
struct iommu *obj = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
iopgtable_clear_entry_all(obj);
|
|
free_pages((unsigned long)obj->iopgd, get_order(IOPGD_TABLE_SIZE));
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
free_irq(irq, obj);
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
release_mem_region(res->start, resource_size(res));
|
|
iounmap(obj->regbase);
|
|
|
|
clk_put(obj->clk);
|
|
dev_info(&pdev->dev, "%s removed\n", obj->name);
|
|
kfree(obj);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver omap_iommu_driver = {
|
|
.probe = omap_iommu_probe,
|
|
.remove = __devexit_p(omap_iommu_remove),
|
|
.driver = {
|
|
.name = "omap-iommu",
|
|
},
|
|
};
|
|
|
|
static void iopte_cachep_ctor(void *iopte)
|
|
{
|
|
clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
|
|
}
|
|
|
|
static int __init omap_iommu_init(void)
|
|
{
|
|
struct kmem_cache *p;
|
|
const unsigned long flags = SLAB_HWCACHE_ALIGN;
|
|
size_t align = 1 << 10; /* L2 pagetable alignement */
|
|
|
|
p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
|
|
iopte_cachep_ctor);
|
|
if (!p)
|
|
return -ENOMEM;
|
|
iopte_cachep = p;
|
|
|
|
return platform_driver_register(&omap_iommu_driver);
|
|
}
|
|
module_init(omap_iommu_init);
|
|
|
|
static void __exit omap_iommu_exit(void)
|
|
{
|
|
kmem_cache_destroy(iopte_cachep);
|
|
|
|
platform_driver_unregister(&omap_iommu_driver);
|
|
}
|
|
module_exit(omap_iommu_exit);
|
|
|
|
MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
|
|
MODULE_ALIAS("platform:omap-iommu");
|
|
MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
|
|
MODULE_LICENSE("GPL v2");
|