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88f489d26b
While removing drmP.h from all .c files the list of header files are also sorted alphabetically. To allow this adjust the header files to pull in the dependencies they needed to allow this. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190608080241.4958-6-sam@ravnborg.org
222 lines
7.3 KiB
C
222 lines
7.3 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SUMO_DPM_H__
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#define __SUMO_DPM_H__
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#include "atom.h"
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#include "radeon.h"
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#define SUMO_MAX_HARDWARE_POWERLEVELS 5
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#define SUMO_PM_NUMBER_OF_TC 15
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struct sumo_pl {
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u32 sclk;
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u32 vddc_index;
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u32 ds_divider_index;
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u32 ss_divider_index;
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u32 allow_gnb_slow;
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u32 sclk_dpm_tdp_limit;
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};
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/* used for the flags field */
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#define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)
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#define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1)
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struct sumo_ps {
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struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
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u32 num_levels;
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/* flags */
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u32 flags;
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};
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#define NUMBER_OF_M3ARB_PARAM_SETS 10
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#define SUMO_MAX_NUMBER_VOLTAGES 4
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struct sumo_disp_clock_voltage_mapping_table {
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u32 num_max_voltage_levels;
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u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
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};
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struct sumo_vid_mapping_entry {
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u16 vid_2bit;
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u16 vid_7bit;
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};
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struct sumo_vid_mapping_table {
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u32 num_entries;
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struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
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};
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struct sumo_sclk_voltage_mapping_entry {
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u32 sclk_frequency;
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u16 vid_2bit;
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u16 rsv;
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};
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struct sumo_sclk_voltage_mapping_table {
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u32 num_max_dpm_entries;
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struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
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};
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struct sumo_sys_info {
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u32 bootup_sclk;
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u32 min_sclk;
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u32 bootup_uma_clk;
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u16 bootup_nb_voltage_index;
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u8 htc_tmp_lmt;
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u8 htc_hyst_lmt;
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struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
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struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;
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struct sumo_vid_mapping_table vid_mapping_table;
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u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
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u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
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u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
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u32 sclk_dpm_boost_margin;
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u32 sclk_dpm_throttle_margin;
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u32 sclk_dpm_tdp_limit_pg;
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u32 gnb_tdp_limit;
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u32 sclk_dpm_tdp_limit_boost;
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u32 boost_sclk;
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u32 boost_vid_2bit;
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bool enable_boost;
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};
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struct sumo_power_info {
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u32 asi;
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u32 pasi;
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u32 bsp;
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u32 bsu;
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u32 pbsp;
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u32 pbsu;
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u32 dsp;
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u32 psp;
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u32 thermal_auto_throttling;
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u32 uvd_m3_arbiter;
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u32 fw_version;
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struct sumo_sys_info sys_info;
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struct sumo_pl acpi_pl;
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struct sumo_pl boot_pl;
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struct sumo_pl boost_pl;
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bool disable_gfx_power_gating_in_uvd;
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bool driver_nbps_policy_disable;
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bool enable_alt_vddnb;
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bool enable_dynamic_m3_arbiter;
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bool enable_gfx_clock_gating;
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bool enable_gfx_power_gating;
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bool enable_mg_clock_gating;
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bool enable_sclk_ds;
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bool enable_auto_thermal_throttling;
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bool enable_dynamic_patch_ps;
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bool enable_dpm;
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bool enable_boost;
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struct radeon_ps current_rps;
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struct sumo_ps current_ps;
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struct radeon_ps requested_rps;
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struct sumo_ps requested_ps;
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};
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#define SUMO_UTC_DFLT_00 0x48
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#define SUMO_UTC_DFLT_01 0x44
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#define SUMO_UTC_DFLT_02 0x44
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#define SUMO_UTC_DFLT_03 0x44
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#define SUMO_UTC_DFLT_04 0x44
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#define SUMO_UTC_DFLT_05 0x44
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#define SUMO_UTC_DFLT_06 0x44
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#define SUMO_UTC_DFLT_07 0x44
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#define SUMO_UTC_DFLT_08 0x44
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#define SUMO_UTC_DFLT_09 0x44
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#define SUMO_UTC_DFLT_10 0x44
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#define SUMO_UTC_DFLT_11 0x44
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#define SUMO_UTC_DFLT_12 0x44
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#define SUMO_UTC_DFLT_13 0x44
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#define SUMO_UTC_DFLT_14 0x44
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#define SUMO_DTC_DFLT_00 0x48
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#define SUMO_DTC_DFLT_01 0x44
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#define SUMO_DTC_DFLT_02 0x44
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#define SUMO_DTC_DFLT_03 0x44
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#define SUMO_DTC_DFLT_04 0x44
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#define SUMO_DTC_DFLT_05 0x44
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#define SUMO_DTC_DFLT_06 0x44
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#define SUMO_DTC_DFLT_07 0x44
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#define SUMO_DTC_DFLT_08 0x44
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#define SUMO_DTC_DFLT_09 0x44
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#define SUMO_DTC_DFLT_10 0x44
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#define SUMO_DTC_DFLT_11 0x44
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#define SUMO_DTC_DFLT_12 0x44
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#define SUMO_DTC_DFLT_13 0x44
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#define SUMO_DTC_DFLT_14 0x44
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#define SUMO_AH_DFLT 5
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#define SUMO_R_DFLT0 70
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#define SUMO_R_DFLT1 70
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#define SUMO_R_DFLT2 70
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#define SUMO_R_DFLT3 70
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#define SUMO_R_DFLT4 100
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#define SUMO_L_DFLT0 0
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#define SUMO_L_DFLT1 20
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#define SUMO_L_DFLT2 20
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#define SUMO_L_DFLT3 20
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#define SUMO_L_DFLT4 20
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#define SUMO_VRC_DFLT 0x30033
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#define SUMO_MGCGTTLOCAL0_DFLT 0
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#define SUMO_MGCGTTLOCAL1_DFLT 0
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#define SUMO_GICST_DFLT 19
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#define SUMO_SST_DFLT 8
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#define SUMO_VOLTAGEDROPT_DFLT 1
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#define SUMO_GFXPOWERGATINGT_DFLT 100
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/* sumo_dpm.c */
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void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);
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void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
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void sumo_clear_vc(struct radeon_device *rdev);
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void sumo_program_sstp(struct radeon_device *rdev);
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void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
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void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
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struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
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ATOM_AVAILABLE_SCLK_LIST *table);
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void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
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struct sumo_vid_mapping_table *vid_mapping_table,
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ATOM_AVAILABLE_SCLK_LIST *table);
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u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
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struct sumo_vid_mapping_table *vid_mapping_table,
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u32 vid_2bit);
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u32 sumo_get_sleep_divider_from_id(u32 id);
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u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
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u32 sclk,
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u32 min_sclk_in_sr);
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/* sumo_smc.c */
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void sumo_initialize_m3_arb(struct radeon_device *rdev);
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void sumo_smu_pg_init(struct radeon_device *rdev);
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void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
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void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
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bool powersaving, bool force_nbps1);
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void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
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void sumo_enable_boost_timer(struct radeon_device *rdev);
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u32 sumo_get_running_fw_version(struct radeon_device *rdev);
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#endif
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