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f301c062dc
Some platforms have flexible mastering capabilities and this needs to be selected at runtime. If the platform has specified private data in the form of the dw_dma_slave then fetch the source and destination masters from here. If this isn't present, default to the previous of 0 and 1. v2: cleanup whitespace Acked-by: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
/*
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* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
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* AVR32 systems.)
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DW_DMAC_H
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#define DW_DMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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};
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/**
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* enum dw_dma_slave_width - DMA slave register access width.
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* @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
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* @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
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* @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
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*/
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enum dw_dma_slave_width {
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DW_DMA_SLAVE_WIDTH_8BIT,
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DW_DMA_SLAVE_WIDTH_16BIT,
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DW_DMA_SLAVE_WIDTH_32BIT,
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};
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @tx_reg: physical address of data register used for
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* memory-to-peripheral transfers
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* @rx_reg: physical address of data register used for
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* peripheral-to-memory transfers
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* @reg_width: peripheral register width
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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dma_addr_t tx_reg;
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dma_addr_t rx_reg;
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enum dw_dma_slave_width reg_width;
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u32 cfg_hi;
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u32 cfg_lo;
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int src_master;
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int dst_master;
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};
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/* Platform-configurable bits in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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#define DWC_CFGH_DST_PER(x) ((x) << 11)
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/* Platform-configurable bits in CFG_LO */
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#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
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#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
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#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
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#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
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#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
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#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
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#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
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#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
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#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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/* DMA API extensions */
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struct dw_cyclic_desc {
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struct dw_desc **desc;
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unsigned long periods;
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void (*period_callback)(void *param);
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void *period_callback_param;
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};
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struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len, size_t period_len,
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enum dma_data_direction direction);
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void dw_dma_cyclic_free(struct dma_chan *chan);
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int dw_dma_cyclic_start(struct dma_chan *chan);
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void dw_dma_cyclic_stop(struct dma_chan *chan);
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dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
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dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
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#endif /* DW_DMAC_H */
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