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27b7d5f3cc
Add AM4372 information to handle L3 error. AM4372 has two clk domains 100f and 200s. Provide flagmux and data associated with it. NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware team, L3 timeout error cannot be cleared the normal way (by setting bit 31 in STDERRLOG_MAIN), instead it may be required to do system reset. L3 error handler can't help in such scenarios. Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as done for undocumented bits. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Darren Etheridge <detheridge@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
23 lines
659 B
Plaintext
23 lines
659 B
Plaintext
* TI - L3 Network On Chip (NoC)
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This version is an implementation of the generic NoC IP
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provided by Arteris.
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Required properties:
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- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
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Should be "ti,omap4-l3-noc" for OMAP4 family
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Should be "ti,dra7-l3-noc" for DRA7 family
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Should be "ti,am4372-l3-noc" for AM43 family
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- reg: Contains L3 register address range for each noc domain.
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- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
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Examples:
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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};
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