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82a5619410
ARM arch timers are tightly coupled with the CPU logic and lose context on platform implementing HW power management when cores are powered down at run-time. Marking the arch timers as C3STOP regardless of power management capabilities causes issues on platforms with no power management, since in that case the arch timers cannot possibly enter states where the timer loses context at runtime and therefore can always be used as a high resolution clockevent device. In order to fix the C3STOP issue in a way compliant with how real HW works, this patch adds a boolean property to the arch timer bindings to define if the arch timer is managed by an always-on power domain. This power domain is present on all ARM platforms to date, and manages HW that must not be turned off, whatever the state of other HW components (eg power controller). On platforms with no power management capabilities, it is the only power domain present, which encompasses and manages power supply for all HW components in the system. If the timer is powered by the always-on power domain, the always-on property must be present in the bindings which means that the timer cannot be shutdown at runtime, so it is not a C3STOP clockevent device. If the timer binding does not contain the always-on property, the timer is assumed to be power-gateable, hence it must be defined as a C3STOP clockevent device. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Magnus Damm <damm@opensource.se> Cc: Marc Carino <marc.ceeeee@gmail.com> Cc: Mark Rutland <mark.rutland@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
85 lines
2.2 KiB
Plaintext
85 lines
2.2 KiB
Plaintext
* ARM architected timer
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ARM cores may have a per-core architected timer, which provides per-cpu timers,
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or a memory mapped architected timer, which provides up to 8 frames with a
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physical and optional virtual timer per frame.
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The per-core architected timer is attached to a GIC to deliver its
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per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
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to deliver its interrupts via SPIs.
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** CP15 Timer node properties:
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- compatible : Should at least contain one of
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"arm,armv7-timer"
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"arm,armv8-timer"
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- interrupts : Interrupt list for secure, non-secure, virtual and
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hypervisor timers, in that order.
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- always-on : a boolean property. If present, the timer is powered through an
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always-on power domain, therefore it never loses context.
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Example:
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timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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};
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** Memory mapped timer node properties:
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- compatible : Should at least contain "arm,armv7-timer-mem".
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- reg : The control frame base address.
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Note that #address-cells, #size-cells, and ranges shall be present to ensure
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the CPU can address a frame's registers.
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A timer node has up to 8 frame sub-nodes, each with the following properties:
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- frame-number: 0 to 7.
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- interrupts : Interrupt list for physical and virtual timers in that order.
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The virtual timer interrupt is optional.
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- reg : The first and second view base addresses in that order. The second view
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base address is optional.
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- status : "disabled" indicates the frame is not available for use. Optional.
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Example:
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timer@f0000000 {
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compatible = "arm,armv7-timer-mem";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xf0000000 0x1000>;
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clock-frequency = <50000000>;
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frame@f0001000 {
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frame-number = <0>
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interrupts = <0 13 0x8>,
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<0 14 0x8>;
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reg = <0xf0001000 0x1000>,
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<0xf0002000 0x1000>;
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};
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frame@f0003000 {
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frame-number = <1>
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interrupts = <0 15 0x8>;
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reg = <0xf0003000 0x1000>;
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status = "disabled";
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};
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};
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