mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 14:26:40 +07:00
b759bd114e
Fix SMP TWD boot regression on r8a7779 based platforms caused by:
4200b16 ARM: shmobile: convert to twd_local_timer_register() interface
After the merge of the above commit it has been impossible to boot
r8a7779 based SoCs with SMP enabled and CONFIG_HAVE_ARM_TWD=y. The
kernel crashes at smp_init_cpus() timing which is before the console
has been initialized, so to the user this looks like a kernel lock up
without any particular error message.
This patch fixes the regression on r8a7779 by moving the TWD
registration code from smp_init_cpus() to sys_timer->init() time.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
159 lines
3.6 KiB
C
159 lines
3.6 KiB
C
/*
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* SMP support for R-Mobile / SH-Mobile - r8a7779 portion
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/common.h>
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#include <mach/r8a7779.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/gic.h>
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#define AVECR IOMEM(0xfe700040)
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static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 1, /* ARM1 */
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.isr_bit = 1, /* ARM1 */
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};
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static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 2, /* ARM2 */
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.isr_bit = 2, /* ARM2 */
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};
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static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 3, /* ARM3 */
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.isr_bit = 3, /* ARM3 */
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};
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static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
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[1] = &r8a7779_ch_cpu1,
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[2] = &r8a7779_ch_cpu2,
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[3] = &r8a7779_ch_cpu3,
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};
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)0xf0000000;
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}
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static DEFINE_SPINLOCK(scu_lock);
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static unsigned long tmp;
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
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void __init r8a7779_register_twd(void)
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{
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twd_local_timer_register(&twd_local_timer);
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}
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#endif
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static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
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{
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void __iomem *scu_base = scu_base_addr();
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spin_lock(&scu_lock);
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tmp = __raw_readl(scu_base + 8);
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tmp &= ~clr;
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tmp |= set;
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spin_unlock(&scu_lock);
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/* disable cache coherency after releasing the lock */
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__raw_writel(tmp, scu_base + 8);
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}
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unsigned int __init r8a7779_get_core_count(void)
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{
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void __iomem *scu_base = scu_base_addr();
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return scu_get_core_count(scu_base);
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}
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int r8a7779_platform_cpu_kill(unsigned int cpu)
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{
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struct r8a7779_pm_ch *ch = NULL;
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int ret = -EIO;
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cpu = cpu_logical_map(cpu);
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/* disable cache coherency */
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modify_scu_cpu_psr(3 << (cpu * 8), 0);
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if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
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ch = r8a7779_ch_cpu[cpu];
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if (ch)
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ret = r8a7779_sysc_power_down(ch);
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return ret ? ret : 1;
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}
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void __cpuinit r8a7779_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
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{
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struct r8a7779_pm_ch *ch = NULL;
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int ret = -EIO;
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cpu = cpu_logical_map(cpu);
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/* enable cache coherency */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
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ch = r8a7779_ch_cpu[cpu];
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if (ch)
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ret = r8a7779_sysc_power_up(ch);
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return ret;
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}
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void __init r8a7779_smp_prepare_cpus(void)
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{
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int cpu = cpu_logical_map(0);
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scu_enable(scu_base_addr());
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/* Map the reset vector (in headsmp.S) */
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__raw_writel(__pa(shmobile_secondary_vector), AVECR);
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/* enable cache coherency on CPU0 */
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modify_scu_cpu_psr(0, 3 << (cpu * 8));
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r8a7779_pm_init();
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/* power off secondary CPUs */
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r8a7779_platform_cpu_kill(1);
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r8a7779_platform_cpu_kill(2);
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r8a7779_platform_cpu_kill(3);
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}
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