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d3db80ca57
Add imx7ulp compatible string. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
58 lines
2.2 KiB
Plaintext
58 lines
2.2 KiB
Plaintext
* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
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The Enhanced Secure Digital Host Controller on Freescale i.MX family
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provides an interface for MMC, SD, and SDIO types of memory cards.
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This file documents differences between the core properties described
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by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
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Required properties:
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- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
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"fsl,imx25-esdhc"
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"fsl,imx35-esdhc"
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"fsl,imx51-esdhc"
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"fsl,imx53-esdhc"
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"fsl,imx6q-usdhc"
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"fsl,imx6sl-usdhc"
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"fsl,imx6sx-usdhc"
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"fsl,imx6ull-usdhc"
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"fsl,imx7d-usdhc"
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"fsl,imx7ulp-usdhc"
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"fsl,imx8qxp-usdhc"
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Optional properties:
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- fsl,wp-controller : Indicate to use controller internal write protection
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- fsl,delay-line : Specify the number of delay cells for override mode.
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This is used to set the clock delay for DLL(Delay Line) on override mode
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to select a proper data sampling window in case the clock quality is not good
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due to signal path is too long on the board. Please refer to eSDHC/uSDHC
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chapter, DLL (Delay Line) section in RM for details.
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- voltage-ranges : Specify the voltage range in case there are software
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transparent level shifters on the outputs of the controller. Two cells are
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required, first cell specifies minimum slot voltage (mV), second cell
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specifies maximum slot voltage (mV). Several ranges could be specified.
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- fsl,tuning-start-tap: Specify the start dealy cell point when send first CMD19
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in tuning procedure.
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- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
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The uSDHC use one delay cell as default increasing step to do tuning process.
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This property allows user to change the tuning step to more than one delay
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cells which is useful for some special boards or cards when the default
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tuning step can't find the proper delay window within limited tuning retries.
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Examples:
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esdhc@70004000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70004000 0x4000>;
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interrupts = <1>;
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fsl,wp-controller;
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};
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esdhc@70008000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70008000 0x4000>;
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interrupts = <2>;
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cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
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wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
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};
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