mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 02:55:11 +07:00
2df11221bd
These new members of the OCTEON III family have some new registers, update some of the definitions for use in follow on patches. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
354 lines
11 KiB
C
354 lines
11 KiB
C
/*
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* Copyright (c) 2003-2016 Cavium Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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*/
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#ifndef __CVMX_CIU3_DEFS_H__
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#define __CVMX_CIU3_DEFS_H__
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#define CVMX_CIU3_FUSE CVMX_ADD_IO_SEG(0x00010100000001A0ull)
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#define CVMX_CIU3_BIST CVMX_ADD_IO_SEG(0x00010100000001C0ull)
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#define CVMX_CIU3_CONST CVMX_ADD_IO_SEG(0x0001010000000220ull)
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#define CVMX_CIU3_CTL CVMX_ADD_IO_SEG(0x00010100000000E0ull)
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#define CVMX_CIU3_DESTX_IO_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000210000ull) + ((offset) & 7) * 8)
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#define CVMX_CIU3_DESTX_PP_INT(offset) (CVMX_ADD_IO_SEG(0x0001010000200000ull) + ((offset) & 255) * 8)
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#define CVMX_CIU3_GSTOP CVMX_ADD_IO_SEG(0x0001010000000140ull)
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#define CVMX_CIU3_IDTX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010000110000ull) + ((offset) & 255) * 8)
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#define CVMX_CIU3_IDTX_IO(offset) (CVMX_ADD_IO_SEG(0x0001010000130000ull) + ((offset) & 255) * 8)
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#define CVMX_CIU3_IDTX_PPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001010000120000ull) + ((block_id) & 255) * 0x20ull)
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#define CVMX_CIU3_INTR_RAM_ECC_CTL CVMX_ADD_IO_SEG(0x0001010000000260ull)
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#define CVMX_CIU3_INTR_RAM_ECC_ST CVMX_ADD_IO_SEG(0x0001010000000280ull)
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#define CVMX_CIU3_INTR_READY CVMX_ADD_IO_SEG(0x00010100000002A0ull)
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#define CVMX_CIU3_INTR_SLOWDOWN CVMX_ADD_IO_SEG(0x0001010000000240ull)
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#define CVMX_CIU3_ISCX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001010080000000ull) + ((offset) & 1048575) * 8)
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#define CVMX_CIU3_ISCX_W1C(offset) (CVMX_ADD_IO_SEG(0x0001010090000000ull) + ((offset) & 1048575) * 8)
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#define CVMX_CIU3_ISCX_W1S(offset) (CVMX_ADD_IO_SEG(0x00010100A0000000ull) + ((offset) & 1048575) * 8)
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#define CVMX_CIU3_NMI CVMX_ADD_IO_SEG(0x0001010000000160ull)
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#define CVMX_CIU3_SISCX(offset) (CVMX_ADD_IO_SEG(0x0001010000220000ull) + ((offset) & 255) * 8)
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#define CVMX_CIU3_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001010000010000ull) + ((offset) & 15) * 8)
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union cvmx_ciu3_bist {
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uint64_t u64;
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struct cvmx_ciu3_bist_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_9_63 : 55;
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uint64_t bist : 9;
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#else
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uint64_t bist : 9;
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uint64_t reserved_9_63 : 55;
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#endif
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} s;
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};
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union cvmx_ciu3_const {
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uint64_t u64;
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struct cvmx_ciu3_const_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t dests_io : 16;
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uint64_t pintsn : 16;
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uint64_t dests_pp : 16;
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uint64_t idt : 16;
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#else
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uint64_t idt : 16;
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uint64_t dests_pp : 16;
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uint64_t pintsn : 16;
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uint64_t dests_io : 16;
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#endif
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} s;
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};
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union cvmx_ciu3_ctl {
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uint64_t u64;
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struct cvmx_ciu3_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_5_63 : 59;
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uint64_t mcd_sel : 2;
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uint64_t iscmem_le : 1;
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uint64_t seq_dis : 1;
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uint64_t cclk_dis : 1;
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#else
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uint64_t cclk_dis : 1;
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uint64_t seq_dis : 1;
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uint64_t iscmem_le : 1;
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uint64_t mcd_sel : 2;
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uint64_t reserved_5_63 : 59;
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#endif
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} s;
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};
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union cvmx_ciu3_destx_io_int {
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uint64_t u64;
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struct cvmx_ciu3_destx_io_int_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_52_63 : 12;
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uint64_t intsn : 20;
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uint64_t reserved_10_31 : 22;
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uint64_t intidt : 8;
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uint64_t newint : 1;
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uint64_t intr : 1;
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#else
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uint64_t intr : 1;
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uint64_t newint : 1;
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uint64_t intidt : 8;
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uint64_t reserved_10_31 : 22;
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uint64_t intsn : 20;
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uint64_t reserved_52_63 : 12;
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#endif
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} s;
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};
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union cvmx_ciu3_destx_pp_int {
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uint64_t u64;
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struct cvmx_ciu3_destx_pp_int_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_52_63 : 12;
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uint64_t intsn : 20;
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uint64_t reserved_10_31 : 22;
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uint64_t intidt : 8;
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uint64_t newint : 1;
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uint64_t intr : 1;
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#else
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uint64_t intr : 1;
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uint64_t newint : 1;
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uint64_t intidt : 8;
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uint64_t reserved_10_31 : 22;
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uint64_t intsn : 20;
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uint64_t reserved_52_63 : 12;
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#endif
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} s;
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};
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union cvmx_ciu3_gstop {
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uint64_t u64;
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struct cvmx_ciu3_gstop_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_1_63 : 63;
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uint64_t gstop : 1;
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#else
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uint64_t gstop : 1;
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uint64_t reserved_1_63 : 63;
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#endif
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} s;
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};
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union cvmx_ciu3_idtx_ctl {
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uint64_t u64;
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struct cvmx_ciu3_idtx_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_52_63 : 12;
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uint64_t intsn : 20;
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uint64_t reserved_4_31 : 28;
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uint64_t intr : 1;
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uint64_t newint : 1;
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uint64_t ip_num : 2;
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#else
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uint64_t ip_num : 2;
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uint64_t newint : 1;
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uint64_t intr : 1;
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uint64_t reserved_4_31 : 28;
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uint64_t intsn : 20;
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uint64_t reserved_52_63 : 12;
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#endif
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} s;
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};
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union cvmx_ciu3_idtx_io {
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uint64_t u64;
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struct cvmx_ciu3_idtx_io_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_5_63 : 59;
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uint64_t io : 5;
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#else
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uint64_t io : 5;
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uint64_t reserved_5_63 : 59;
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#endif
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} s;
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};
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union cvmx_ciu3_idtx_ppx {
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uint64_t u64;
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struct cvmx_ciu3_idtx_ppx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_48_63 : 16;
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uint64_t pp : 48;
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#else
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uint64_t pp : 48;
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uint64_t reserved_48_63 : 16;
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#endif
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} s;
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};
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union cvmx_ciu3_intr_ram_ecc_ctl {
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uint64_t u64;
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struct cvmx_ciu3_intr_ram_ecc_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_3_63 : 61;
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uint64_t flip_synd : 2;
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uint64_t ecc_ena : 1;
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#else
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uint64_t ecc_ena : 1;
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uint64_t flip_synd : 2;
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uint64_t reserved_3_63 : 61;
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#endif
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} s;
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};
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union cvmx_ciu3_intr_ram_ecc_st {
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uint64_t u64;
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struct cvmx_ciu3_intr_ram_ecc_st_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_52_63 : 12;
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uint64_t addr : 20;
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uint64_t reserved_6_31 : 26;
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uint64_t sisc_dbe : 1;
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uint64_t sisc_sbe : 1;
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uint64_t idt_dbe : 1;
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uint64_t idt_sbe : 1;
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uint64_t isc_dbe : 1;
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uint64_t isc_sbe : 1;
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#else
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uint64_t isc_sbe : 1;
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uint64_t isc_dbe : 1;
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uint64_t idt_sbe : 1;
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uint64_t idt_dbe : 1;
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uint64_t sisc_sbe : 1;
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uint64_t sisc_dbe : 1;
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uint64_t reserved_6_31 : 26;
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uint64_t addr : 20;
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uint64_t reserved_52_63 : 12;
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#endif
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} s;
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};
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union cvmx_ciu3_intr_ready {
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uint64_t u64;
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struct cvmx_ciu3_intr_ready_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_46_63 : 18;
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uint64_t index : 14;
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uint64_t reserved_1_31 : 31;
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uint64_t ready : 1;
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#else
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uint64_t ready : 1;
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uint64_t reserved_1_31 : 31;
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uint64_t index : 14;
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uint64_t reserved_46_63 : 18;
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#endif
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} s;
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};
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union cvmx_ciu3_intr_slowdown {
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uint64_t u64;
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struct cvmx_ciu3_intr_slowdown_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_3_63 : 61;
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uint64_t ctl : 3;
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#else
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uint64_t ctl : 3;
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uint64_t reserved_3_63 : 61;
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#endif
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} s;
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};
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union cvmx_ciu3_iscx_ctl {
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uint64_t u64;
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struct cvmx_ciu3_iscx_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_24_63 : 40;
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uint64_t idt : 8;
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uint64_t imp : 1;
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uint64_t reserved_2_14 : 13;
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uint64_t en : 1;
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uint64_t raw : 1;
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#else
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uint64_t raw : 1;
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uint64_t en : 1;
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uint64_t reserved_2_14 : 13;
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uint64_t imp : 1;
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uint64_t idt : 8;
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uint64_t reserved_24_63 : 40;
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#endif
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} s;
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};
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union cvmx_ciu3_iscx_w1c {
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uint64_t u64;
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struct cvmx_ciu3_iscx_w1c_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_2_63 : 62;
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uint64_t en : 1;
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uint64_t raw : 1;
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#else
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uint64_t raw : 1;
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uint64_t en : 1;
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uint64_t reserved_2_63 : 62;
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#endif
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} s;
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};
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union cvmx_ciu3_iscx_w1s {
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uint64_t u64;
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struct cvmx_ciu3_iscx_w1s_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_2_63 : 62;
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uint64_t en : 1;
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uint64_t raw : 1;
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#else
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uint64_t raw : 1;
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uint64_t en : 1;
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uint64_t reserved_2_63 : 62;
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#endif
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} s;
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};
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union cvmx_ciu3_nmi {
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uint64_t u64;
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struct cvmx_ciu3_nmi_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_48_63 : 16;
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uint64_t nmi : 48;
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#else
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uint64_t nmi : 48;
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uint64_t reserved_48_63 : 16;
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#endif
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} s;
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};
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union cvmx_ciu3_siscx {
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uint64_t u64;
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struct cvmx_ciu3_siscx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t en : 64;
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#else
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uint64_t en : 64;
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#endif
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} s;
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};
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union cvmx_ciu3_timx {
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uint64_t u64;
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struct cvmx_ciu3_timx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_37_63 : 27;
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uint64_t one_shot : 1;
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uint64_t len : 36;
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#else
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uint64_t len : 36;
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uint64_t one_shot : 1;
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uint64_t reserved_37_63 : 27;
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#endif
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} s;
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};
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#endif
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