mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-25 03:09:56 +07:00
93b694d096
New driver: Cadence MHDP8546 DisplayPort bridge driver core: - cross-driver scatterlist cleanups - devm_drm conversions - remove drm_dev_init - devm_drm_dev_alloc conversion ttm: - lots of refactoring and cleanups bridges: - chained bridge support in more drivers panel: - misc new panels scheduler: - cleanup priority levels displayport: - refactor i915 code into helpers for nouveau i915: - split into display and GT trees - WW locking refactoring in GEM - execbuf2 extension mechanism - syncobj timeline support - GEN 12 HOBL display powersaving - Rocket Lake display additions - Disable FBC on Tigerlake - Tigerlake Type-C + DP improvements - Hotplug interrupt refactoring amdgpu: - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support for DC - Plane rotation enabled - TMZ state info ioctl - PCIe DPC recovery support - DC interrupt handling refactor - OLED panel fixes amdkfd: - add SMI events for thermal throttling - SMI interface events ioctl update - process eviction counters radeon: - move to dma_ for allocations - expose sclk via sysfs msm: - DSI support for sm8150/sm8250 - per-process GPU pagetable support - Displayport support mediatek: - move HDMI phy driver to PHY - convert mtk-dpi to bridge API - disable mt2701 tmds tegra: - bridge support exynos: - misc cleanups vc4: - dual display cleanups ast: - cleanups gma500: - conversion to GPIOd API hisilicon: - misc reworks ingenic: - clock handling and format improvements mcde: - DSI support mgag200: - desktop g200 support mxsfb: - i.MX7 + i.MX8M - alpha plane support panfrost: - devfreq support - amlogic SoC support ps8640: - EDID from eDP retrieval tidss: - AM65xx YUV workaround virtio: - virtio-gpu exported resources rcar-du: - R8A7742, R8A774E1 and R8A77961 support - YUV planar format fixes - non-visible plane handling - VSP device reference count fix - Kconfig fix to avoid displaying disabled options in .config -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJfh579AAoJEAx081l5xIa+GqoP/0amz+ZN7y/L7+f32CRinJ7/ 3e4xjXNDmtWG4Whe/WKjlYmbAcvSdWV/4HYpurW2BFJnOAB/5lIqYcS/PyqErPzA w4EpRoJ+ZdFgmlDH0vdsDwPLT/HFmhUN9AopNkoZpbSMxrManSj5QgmePXyiKReP Q+ZAK5UW5AdOVY4bgXUSEkVq2eilCLXf+bSBR/LrVQuNgu7GULX8SIy/Y1CuMtv8 LgzzjLKfIZaIWC+F/RU7BxJ7YnrVq7z7yXnUx8j2416+k/Wwe+BeSUCSZstT7q9G UkX8jWfR7ZKqhwP+UQeSwDbHkALz7lv88nyjQdxJZ3SrXRe4hy14YjxnR4maeNAj 3TAYSdcAMWyRHqeEZIZ7Hj5sQtTq5OZAoIjxzH3vpVdAnnAkcWoF77pqxV8XPqTC nw40DihAxQOshGwMkjd5DqkEwnMv43Hs1WTVYu9dPTOfOdqPNt+Vqp7Xl9Z46+kV k6PDcx60T9ayDW1QZ6MoIXHta9E7ixzu7gYBL3vP4LuporY0uNG3bzF3CMvof1BK sHYcYTdZkqbTD2d6rHV+TbpPQXgTtlej9qVlQM4SeX37Xtc7LxCYpnpUHKz2S/fK 1vyeGPgdytHblwlxwZOPZ4R2I/HTfnITdr4kMcJHhxAsEewfW1Rd4+stQqVJ2Mph Vz+CFP2BngivGFz5vuky =4H8J -----END PGP SIGNATURE----- Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Not a major amount of change, the i915 trees got split into display and gt trees to better facilitate higher level review, and there's a major refactoring of i915 GEM locking to use more core kernel concepts (like ww-mutexes). msm gets per-process pagetables, older AMD SI cards get DC support, nouveau got a bump in displayport support with common code extraction from i915. Outside of drm this contains a couple of patches for hexint moduleparams which you've acked, and a virtio common code tree that you should also get via it's regular path. New driver: - Cadence MHDP8546 DisplayPort bridge driver core: - cross-driver scatterlist cleanups - devm_drm conversions - remove drm_dev_init - devm_drm_dev_alloc conversion ttm: - lots of refactoring and cleanups bridges: - chained bridge support in more drivers panel: - misc new panels scheduler: - cleanup priority levels displayport: - refactor i915 code into helpers for nouveau i915: - split into display and GT trees - WW locking refactoring in GEM - execbuf2 extension mechanism - syncobj timeline support - GEN 12 HOBL display powersaving - Rocket Lake display additions - Disable FBC on Tigerlake - Tigerlake Type-C + DP improvements - Hotplug interrupt refactoring amdgpu: - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support for DC - Plane rotation enabled - TMZ state info ioctl - PCIe DPC recovery support - DC interrupt handling refactor - OLED panel fixes amdkfd: - add SMI events for thermal throttling - SMI interface events ioctl update - process eviction counters radeon: - move to dma_ for allocations - expose sclk via sysfs msm: - DSI support for sm8150/sm8250 - per-process GPU pagetable support - Displayport support mediatek: - move HDMI phy driver to PHY - convert mtk-dpi to bridge API - disable mt2701 tmds tegra: - bridge support exynos: - misc cleanups vc4: - dual display cleanups ast: - cleanups gma500: - conversion to GPIOd API hisilicon: - misc reworks ingenic: - clock handling and format improvements mcde: - DSI support mgag200: - desktop g200 support mxsfb: - i.MX7 + i.MX8M - alpha plane support panfrost: - devfreq support - amlogic SoC support ps8640: - EDID from eDP retrieval tidss: - AM65xx YUV workaround virtio: - virtio-gpu exported resources rcar-du: - R8A7742, R8A774E1 and R8A77961 support - YUV planar format fixes - non-visible plane handling - VSP device reference count fix - Kconfig fix to avoid displaying disabled options in .config" * tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm: (1494 commits) drm/ingenic: Fix bad revert drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init drm/amdgpu: Remove warning for virtual_display drm/amdgpu: kfd_initialized can be static drm/amd/pm: setup APU dpm clock table in SMU HW initialization drm/amdgpu: prevent spurious warning drm/amdgpu/swsmu: fix ARC build errors drm/amd/display: Fix OPTC_DATA_FORMAT programming drm/amd/display: Don't allow pstate if no support in blank drm/panfrost: increase readl_relaxed_poll_timeout values MAINTAINERS: Update entry for st7703 driver after the rename Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached" drm/amd/display: HDMI remote sink need mode validation for Linux drm/amd/display: Change to correct unit on audio rate drm/amd/display: Avoid set zero in the requested clk drm/amdgpu: align frag_end to covered address space drm/amdgpu: fix NULL pointer dereference for Renoir drm/vmwgfx: fix regression in thp code due to ttm init refactor. drm/amdgpu/swsmu: add interrupt work handler for smu11 parts drm/amdgpu/swsmu: add interrupt work function ...
277 lines
10 KiB
C
277 lines
10 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
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#ifndef AMDGPU_AMDKFD_H_INCLUDED
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#define AMDGPU_AMDKFD_H_INCLUDED
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/kthread.h>
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#include <linux/workqueue.h>
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#include <kgd_kfd_interface.h>
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#include <drm/ttm/ttm_execbuf_util.h>
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#include "amdgpu_sync.h"
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#include "amdgpu_vm.h"
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extern uint64_t amdgpu_amdkfd_total_mem_size;
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struct amdgpu_device;
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struct kfd_bo_va_list {
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struct list_head bo_list;
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struct amdgpu_bo_va *bo_va;
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void *kgd_dev;
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bool is_mapped;
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uint64_t va;
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uint64_t pte_flags;
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};
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struct kgd_mem {
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struct mutex lock;
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struct amdgpu_bo *bo;
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struct list_head bo_va_list;
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/* protected by amdkfd_process_info.lock */
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struct ttm_validate_buffer validate_list;
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struct ttm_validate_buffer resv_list;
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uint32_t domain;
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unsigned int mapped_to_gpu_memory;
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uint64_t va;
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uint32_t alloc_flags;
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atomic_t invalid;
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struct amdkfd_process_info *process_info;
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struct amdgpu_sync sync;
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bool aql_queue;
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bool is_imported;
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};
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/* KFD Memory Eviction */
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struct amdgpu_amdkfd_fence {
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struct dma_fence base;
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struct mm_struct *mm;
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spinlock_t lock;
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char timeline_name[TASK_COMM_LEN];
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};
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struct amdgpu_kfd_dev {
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struct kfd_dev *dev;
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uint64_t vram_used;
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};
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enum kgd_engine_type {
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KGD_ENGINE_PFP = 1,
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KGD_ENGINE_ME,
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KGD_ENGINE_CE,
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KGD_ENGINE_MEC1,
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KGD_ENGINE_MEC2,
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KGD_ENGINE_RLC,
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KGD_ENGINE_SDMA1,
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KGD_ENGINE_SDMA2,
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KGD_ENGINE_MAX
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};
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struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
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struct mm_struct *mm);
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bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
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struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
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int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
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struct amdkfd_process_info {
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/* List head of all VMs that belong to a KFD process */
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struct list_head vm_list_head;
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/* List head for all KFD BOs that belong to a KFD process. */
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struct list_head kfd_bo_list;
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/* List of userptr BOs that are valid or invalid */
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struct list_head userptr_valid_list;
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struct list_head userptr_inval_list;
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/* Lock to protect kfd_bo_list */
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struct mutex lock;
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/* Number of VMs */
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unsigned int n_vms;
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/* Eviction Fence */
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struct amdgpu_amdkfd_fence *eviction_fence;
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/* MMU-notifier related fields */
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atomic_t evicted_bos;
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struct delayed_work restore_userptr_work;
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struct pid *pid;
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};
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int amdgpu_amdkfd_init(void);
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void amdgpu_amdkfd_fini(void);
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void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
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int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
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void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
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const void *ih_ring_entry);
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void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
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void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
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void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
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int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
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int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
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uint32_t vmid, uint64_t gpu_addr,
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uint32_t *ib_cmd, uint32_t ib_len);
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void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
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bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
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int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid);
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int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid);
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bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
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int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
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int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
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void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
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int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
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int queue_bit);
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/* Shared API */
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int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
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void **mem_obj, uint64_t *gpu_addr,
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void **cpu_ptr, bool mqd_gfx9);
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void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
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int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj);
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void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj);
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int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
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int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
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uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
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enum kgd_engine_type type);
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void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
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struct kfd_local_mem_info *mem_info);
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uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd);
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uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
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void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
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int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
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struct kgd_dev **dmabuf_kgd,
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uint64_t *bo_size, void *metadata_buffer,
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size_t buffer_size, uint32_t *metadata_size,
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uint32_t *flags);
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uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
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uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
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uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd);
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uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
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uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
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uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
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int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd);
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uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
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/* Read user wptr from a specified user address space with page fault
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* disabled. The memory must be pinned and mapped to the hardware when
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* this is called in hqd_load functions, so it should never fault in
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* the first place. This resolves a circular lock dependency involving
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* four locks, including the DQM lock and mmap_lock.
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*/
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#define read_user_wptr(mmptr, wptr, dst) \
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({ \
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bool valid = false; \
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if ((mmptr) && (wptr)) { \
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pagefault_disable(); \
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if ((mmptr) == current->mm) { \
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valid = !get_user((dst), (wptr)); \
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} else if (current->flags & PF_KTHREAD) { \
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kthread_use_mm(mmptr); \
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valid = !get_user((dst), (wptr)); \
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kthread_unuse_mm(mmptr); \
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} \
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pagefault_enable(); \
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} \
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valid; \
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})
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/* GPUVM API */
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int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, u32 pasid,
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void **vm, void **process_info,
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struct dma_fence **ef);
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int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
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struct file *filp, u32 pasid,
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void **vm, void **process_info,
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struct dma_fence **ef);
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void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
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struct amdgpu_vm *vm);
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void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
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void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
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uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
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int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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struct kgd_dev *kgd, uint64_t va, uint64_t size,
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void *vm, struct kgd_mem **mem,
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uint64_t *offset, uint32_t flags);
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int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
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struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size);
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int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
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struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
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int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
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struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
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int amdgpu_amdkfd_gpuvm_sync_memory(
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struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
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int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
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struct kgd_mem *mem, void **kptr, uint64_t *size);
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int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
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struct dma_fence **ef);
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int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
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struct kfd_vm_fault_info *info);
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int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
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struct dma_buf *dmabuf,
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uint64_t va, void *vm,
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struct kgd_mem **mem, uint64_t *size,
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uint64_t *mmap_offset);
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void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
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void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
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int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
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struct tile_config *config);
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/* KGD2KFD callbacks */
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int kgd2kfd_init(void);
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void kgd2kfd_exit(void);
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struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
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unsigned int asic_type, bool vf);
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bool kgd2kfd_device_init(struct kfd_dev *kfd,
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struct drm_device *ddev,
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const struct kgd2kfd_shared_resources *gpu_resources);
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void kgd2kfd_device_exit(struct kfd_dev *kfd);
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void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
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int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
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int kgd2kfd_pre_reset(struct kfd_dev *kfd);
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int kgd2kfd_post_reset(struct kfd_dev *kfd);
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void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
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int kgd2kfd_quiesce_mm(struct mm_struct *mm);
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int kgd2kfd_resume_mm(struct mm_struct *mm);
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int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
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struct dma_fence *fence);
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void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
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void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask);
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#endif /* AMDGPU_AMDKFD_H_INCLUDED */
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