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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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34d1324edd
Support for boards based on Techwell TW5864 chip which provides multichannel video & audio grabbing and encoding (H.264, MJPEG, ADPCM G.726). This submission implements only H.264 encoding of all channels at D1 resolution. Thanks to Mark Thompson <sw@jkqxz.net> for help, and for contribution of H.264 startcode emulation prevention code. Signed-off-by: Andrey Utkin <andrey.utkin@corp.bluecherry.net> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
206 lines
5.5 KiB
C
206 lines
5.5 KiB
C
/*
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* TW5864 driver - common header file
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*
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* Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/pci.h>
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#include <linux/videodev2.h>
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#include <linux/notifier.h>
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#include <linux/delay.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <media/v4l2-common.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/videobuf2-dma-sg.h>
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#include "tw5864-reg.h"
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#define PCI_DEVICE_ID_TECHWELL_5864 0x5864
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#define TW5864_NORMS V4L2_STD_ALL
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/* ----------------------------------------------------------- */
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/* card configuration */
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#define TW5864_INPUTS 4
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/* The TW5864 uses 192 (16x12) detection cells in full screen for motion
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* detection. Each detection cell is composed of 44 pixels and 20 lines for
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* NTSC and 24 lines for PAL.
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*/
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#define MD_CELLS_HOR 16
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#define MD_CELLS_VERT 12
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#define MD_CELLS (MD_CELLS_HOR * MD_CELLS_VERT)
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#define H264_VLC_BUF_SIZE 0x80000
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#define H264_MV_BUF_SIZE 0x2000 /* device writes 5396 bytes */
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#define QP_VALUE 28
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#define MAX_GOP_SIZE 255
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#define GOP_SIZE MAX_GOP_SIZE
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enum resolution {
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D1 = 1,
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HD1 = 2, /* half d1 - 360x(240|288) */
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CIF = 3,
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QCIF = 4,
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};
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/* ----------------------------------------------------------- */
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/* device / file handle status */
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struct tw5864_dev; /* forward delclaration */
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/* buffer for one video/vbi/ts frame */
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struct tw5864_buf {
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struct vb2_v4l2_buffer vb;
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struct list_head list;
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unsigned int size;
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};
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struct tw5864_dma_buf {
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void *addr;
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dma_addr_t dma_addr;
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};
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enum tw5864_vid_std {
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STD_NTSC = 0, /* NTSC (M) */
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STD_PAL = 1, /* PAL (B, D, G, H, I) */
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STD_SECAM = 2, /* SECAM */
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STD_NTSC443 = 3, /* NTSC4.43 */
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STD_PAL_M = 4, /* PAL (M) */
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STD_PAL_CN = 5, /* PAL (CN) */
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STD_PAL_60 = 6, /* PAL 60 */
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STD_INVALID = 7,
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STD_AUTO = 7,
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};
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struct tw5864_input {
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int nr; /* input number */
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struct tw5864_dev *root;
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struct mutex lock; /* used for vidq and vdev */
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spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */
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struct video_device vdev;
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struct v4l2_ctrl_handler hdl;
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struct vb2_queue vidq;
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struct list_head active;
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enum resolution resolution;
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unsigned int width, height;
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unsigned int frame_seqno;
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unsigned int frame_gop_seqno;
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unsigned int h264_idr_pic_id;
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int enabled;
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enum tw5864_vid_std std;
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v4l2_std_id v4l2_std;
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int tail_nb_bits;
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u8 tail;
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u8 *buf_cur_ptr;
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int buf_cur_space_left;
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u32 reg_interlacing;
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u32 reg_vlc;
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u32 reg_dsp_codec;
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u32 reg_dsp;
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u32 reg_emu;
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u32 reg_dsp_qp;
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u32 reg_dsp_ref_mvp_lambda;
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u32 reg_dsp_i4x4_weight;
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u32 buf_id;
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struct tw5864_buf *vb;
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struct v4l2_ctrl *md_threshold_grid_ctrl;
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u16 md_threshold_grid_values[12 * 16];
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int qp;
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int gop;
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/*
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* In (1/MAX_FPS) units.
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* For max FPS (default), set to 1.
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* For 1 FPS, set to e.g. 32.
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*/
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int frame_interval;
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unsigned long new_frame_deadline;
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};
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struct tw5864_h264_frame {
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struct tw5864_dma_buf vlc;
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struct tw5864_dma_buf mv;
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int vlc_len;
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u32 checksum;
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struct tw5864_input *input;
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u64 timestamp;
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unsigned int seqno;
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unsigned int gop_seqno;
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};
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/* global device status */
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struct tw5864_dev {
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spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */
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struct v4l2_device v4l2_dev;
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struct tw5864_input inputs[TW5864_INPUTS];
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#define H264_BUF_CNT 4
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struct tw5864_h264_frame h264_buf[H264_BUF_CNT];
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int h264_buf_r_index;
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int h264_buf_w_index;
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struct tasklet_struct tasklet;
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int encoder_busy;
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/* Input number to check next for ready raw picture (in RR fashion) */
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int next_input;
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/* pci i/o */
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char name[64];
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struct pci_dev *pci;
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void __iomem *mmio;
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u32 irqmask;
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};
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#define tw_readl(reg) readl(dev->mmio + reg)
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#define tw_mask_readl(reg, mask) \
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(tw_readl(reg) & (mask))
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#define tw_mask_shift_readl(reg, mask, shift) \
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(tw_mask_readl((reg), ((mask) << (shift))) >> (shift))
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#define tw_writel(reg, value) writel((value), dev->mmio + reg)
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#define tw_mask_writel(reg, mask, value) \
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tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask)))
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#define tw_mask_shift_writel(reg, mask, shift, value) \
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tw_mask_writel((reg), ((mask) << (shift)), ((value) << (shift)))
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#define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit))
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#define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit))
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u8 tw5864_indir_readb(struct tw5864_dev *dev, u16 addr);
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#define tw_indir_readb(addr) tw5864_indir_readb(dev, addr)
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void tw5864_indir_writeb(struct tw5864_dev *dev, u16 addr, u8 data);
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#define tw_indir_writeb(addr, data) tw5864_indir_writeb(dev, addr, data)
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void tw5864_irqmask_apply(struct tw5864_dev *dev);
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int tw5864_video_init(struct tw5864_dev *dev, int *video_nr);
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void tw5864_video_fini(struct tw5864_dev *dev);
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void tw5864_prepare_frame_headers(struct tw5864_input *input);
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void tw5864_h264_put_stream_header(u8 **buf, size_t *space_left, int qp,
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int width, int height);
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void tw5864_h264_put_slice_header(u8 **buf, size_t *space_left,
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unsigned int idr_pic_id,
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unsigned int frame_gop_seqno,
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int *tail_nb_bits, u8 *tail);
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void tw5864_request_encoded_frame(struct tw5864_input *input);
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