mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 07:46:53 +07:00
0a5b7b0bd9
This adds spinlocks to protect access to other indirect register apertures. These indirect spaces are used pretty infrequently and we haven't had an reported problems, but better safe than sorry. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
577 lines
16 KiB
C
577 lines
16 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "rs400d.h"
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/* This files gather functions specifics to : rs400,rs480 */
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static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
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void rs400_gart_adjust_size(struct radeon_device *rdev)
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{
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/* Check gart size */
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switch (rdev->mc.gtt_size/(1024*1024)) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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DRM_ERROR("Unable to use IGP GART size %uM\n",
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(unsigned)(rdev->mc.gtt_size >> 20));
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DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
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DRM_ERROR("Forcing to 32M GART size\n");
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rdev->mc.gtt_size = 32 * 1024 * 1024;
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return;
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}
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}
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void rs400_gart_tlb_flush(struct radeon_device *rdev)
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{
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uint32_t tmp;
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unsigned int timeout = rdev->usec_timeout;
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WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
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do {
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tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
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if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
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break;
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DRM_UDELAY(1);
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timeout--;
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} while (timeout > 0);
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WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
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}
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int rs400_gart_init(struct radeon_device *rdev)
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{
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int r;
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if (rdev->gart.ptr) {
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WARN(1, "RS400 GART already initialized\n");
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return 0;
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}
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/* Check gart size */
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switch(rdev->mc.gtt_size / (1024 * 1024)) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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case 1024:
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case 2048:
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break;
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default:
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return -EINVAL;
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}
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/* Initialize common gart structure */
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r = radeon_gart_init(rdev);
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if (r)
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return r;
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if (rs400_debugfs_pcie_gart_info_init(rdev))
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DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
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rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
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return radeon_gart_table_ram_alloc(rdev);
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}
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int rs400_gart_enable(struct radeon_device *rdev)
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{
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uint32_t size_reg;
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uint32_t tmp;
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radeon_gart_restore(rdev);
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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/* Check gart size */
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switch(rdev->mc.gtt_size / (1024 * 1024)) {
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case 32:
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size_reg = RS480_VA_SIZE_32MB;
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break;
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case 64:
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size_reg = RS480_VA_SIZE_64MB;
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break;
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case 128:
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size_reg = RS480_VA_SIZE_128MB;
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break;
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case 256:
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size_reg = RS480_VA_SIZE_256MB;
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break;
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case 512:
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size_reg = RS480_VA_SIZE_512MB;
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break;
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case 1024:
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size_reg = RS480_VA_SIZE_1GB;
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break;
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case 2048:
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size_reg = RS480_VA_SIZE_2GB;
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break;
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default:
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return -EINVAL;
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}
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/* It should be fine to program it to max value */
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if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
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WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
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} else {
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WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
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WREG32(RS480_AGP_BASE_2, 0);
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}
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tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
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tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
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if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
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WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
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tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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} else {
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WREG32(RADEON_MC_AGP_LOCATION, tmp);
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tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
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WREG32(RADEON_BUS_CNTL, tmp);
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}
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/* Table should be in 32bits address space so ignore bits above. */
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tmp = (u32)rdev->gart.table_addr & 0xfffff000;
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tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
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WREG32_MC(RS480_GART_BASE, tmp);
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/* TODO: more tweaking here */
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WREG32_MC(RS480_GART_FEATURE_ID,
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(RS480_TLB_ENABLE |
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RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
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/* Disable snooping */
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WREG32_MC(RS480_AGP_MODE_CNTL,
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(1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
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/* Disable AGP mode */
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/* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
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* AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
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if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
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tmp = RREG32_MC(RS480_MC_MISC_CNTL);
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tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
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WREG32_MC(RS480_MC_MISC_CNTL, tmp);
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} else {
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tmp = RREG32_MC(RS480_MC_MISC_CNTL);
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tmp |= RS480_GART_INDEX_REG_EN;
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WREG32_MC(RS480_MC_MISC_CNTL, tmp);
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}
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/* Enable gart */
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WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
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rs400_gart_tlb_flush(rdev);
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DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
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(unsigned)(rdev->mc.gtt_size >> 20),
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(unsigned long long)rdev->gart.table_addr);
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rdev->gart.ready = true;
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return 0;
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}
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void rs400_gart_disable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
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}
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void rs400_gart_fini(struct radeon_device *rdev)
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{
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radeon_gart_fini(rdev);
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rs400_gart_disable(rdev);
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radeon_gart_table_ram_free(rdev);
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}
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#define RS400_PTE_WRITEABLE (1 << 2)
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#define RS400_PTE_READABLE (1 << 3)
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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uint32_t entry;
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u32 *gtt = rdev->gart.ptr;
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if (i < 0 || i > rdev->gart.num_gpu_pages) {
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return -EINVAL;
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}
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entry = (lower_32_bits(addr) & PAGE_MASK) |
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((upper_32_bits(addr) & 0xff) << 4) |
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RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
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entry = cpu_to_le32(entry);
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gtt[i] = entry;
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return 0;
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}
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int rs400_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32(RADEON_MC_STATUS);
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if (tmp & RADEON_MC_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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}
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return -1;
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}
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static void rs400_gpu_init(struct radeon_device *rdev)
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{
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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if (rs400_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "rs400: Failed to wait MC idle while "
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"programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
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}
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}
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static void rs400_mc_init(struct radeon_device *rdev)
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{
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u64 base;
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rs400_gart_adjust_size(rdev);
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rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
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/* DDR for all card after R300 & IGP */
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_width = 128;
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r100_vram_init_sizes(rdev);
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base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
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radeon_vram_location(rdev, &rdev->mc, base);
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rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
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{
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unsigned long flags;
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uint32_t r;
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spin_lock_irqsave(&rdev->mc_idx_lock, flags);
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WREG32(RS480_NB_MC_INDEX, reg & 0xff);
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r = RREG32(RS480_NB_MC_DATA);
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WREG32(RS480_NB_MC_INDEX, 0xff);
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spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
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return r;
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}
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void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
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{
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unsigned long flags;
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spin_lock_irqsave(&rdev->mc_idx_lock, flags);
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WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
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WREG32(RS480_NB_MC_DATA, (v));
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WREG32(RS480_NB_MC_INDEX, 0xff);
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spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
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}
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#if defined(CONFIG_DEBUG_FS)
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static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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uint32_t tmp;
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tmp = RREG32(RADEON_HOST_PATH_CNTL);
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seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
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tmp = RREG32(RADEON_BUS_CNTL);
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seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
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if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
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tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
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seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
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seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
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seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
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seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
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tmp = RREG32(RS690_HDP_FB_LOCATION);
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seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
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} else {
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tmp = RREG32(RADEON_AGP_BASE);
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seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
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tmp = RREG32(RS480_AGP_BASE_2);
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seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
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tmp = RREG32(RADEON_MC_AGP_LOCATION);
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seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
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}
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tmp = RREG32_MC(RS480_GART_BASE);
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seq_printf(m, "GART_BASE 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_GART_FEATURE_ID);
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seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
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seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_MC_MISC_CNTL);
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seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
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tmp = RREG32_MC(0x5F);
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seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
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seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
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tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
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seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
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tmp = RREG32_MC(0x3B);
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seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
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tmp = RREG32_MC(0x3C);
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seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
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tmp = RREG32_MC(0x30);
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seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
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tmp = RREG32_MC(0x31);
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seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
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tmp = RREG32_MC(0x32);
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seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
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tmp = RREG32_MC(0x33);
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seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
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tmp = RREG32_MC(0x34);
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seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
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tmp = RREG32_MC(0x35);
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seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
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tmp = RREG32_MC(0x36);
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seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
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tmp = RREG32_MC(0x37);
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seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
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return 0;
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}
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static struct drm_info_list rs400_gart_info_list[] = {
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{"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
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};
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#endif
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static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
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{
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#if defined(CONFIG_DEBUG_FS)
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return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
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#else
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return 0;
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#endif
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}
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static void rs400_mc_program(struct radeon_device *rdev)
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{
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struct r100_mc_save save;
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/* Stops all mc clients */
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r100_mc_stop(rdev, &save);
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/* Wait for mc idle */
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if (rs400_mc_wait_for_idle(rdev))
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dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
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WREG32(R_000148_MC_FB_LOCATION,
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S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
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S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
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r100_mc_resume(rdev, &save);
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}
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static int rs400_startup(struct radeon_device *rdev)
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{
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int r;
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r100_set_common_regs(rdev);
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rs400_mc_program(rdev);
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/* Resume clock */
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r300_clock_startup(rdev);
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/* Initialize GPU configuration (# pipes, ...) */
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rs400_gpu_init(rdev);
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r100_enable_bm(rdev);
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/* Initialize GART (initialize after TTM so we can allocate
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* memory through TTM but finalize after TTM) */
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r = rs400_gart_enable(rdev);
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if (r)
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return r;
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/* allocate wb buffer */
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r = radeon_wb_init(rdev);
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if (r)
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return r;
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r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
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if (r) {
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
/* Enable IRQ */
|
|
if (!rdev->irq.installed) {
|
|
r = radeon_irq_kms_init(rdev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
r100_irq_set(rdev);
|
|
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
|
/* 1M ring buffer */
|
|
r = r100_cp_init(rdev, 1024 * 1024);
|
|
if (r) {
|
|
dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
r = radeon_ib_pool_init(rdev);
|
|
if (r) {
|
|
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int rs400_resume(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
/* Make sur GART are not working */
|
|
rs400_gart_disable(rdev);
|
|
/* Resume clock before doing reset */
|
|
r300_clock_startup(rdev);
|
|
/* setup MC before calling post tables */
|
|
rs400_mc_program(rdev);
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (radeon_asic_reset(rdev)) {
|
|
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
RREG32(R_0007C0_CP_STAT));
|
|
}
|
|
/* post */
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
/* Resume clock after posting */
|
|
r300_clock_startup(rdev);
|
|
/* Initialize surface registers */
|
|
radeon_surface_init(rdev);
|
|
|
|
rdev->accel_working = true;
|
|
r = rs400_startup(rdev);
|
|
if (r) {
|
|
rdev->accel_working = false;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
int rs400_suspend(struct radeon_device *rdev)
|
|
{
|
|
r100_cp_disable(rdev);
|
|
radeon_wb_disable(rdev);
|
|
r100_irq_disable(rdev);
|
|
rs400_gart_disable(rdev);
|
|
return 0;
|
|
}
|
|
|
|
void rs400_fini(struct radeon_device *rdev)
|
|
{
|
|
r100_cp_fini(rdev);
|
|
radeon_wb_fini(rdev);
|
|
radeon_ib_pool_fini(rdev);
|
|
radeon_gem_fini(rdev);
|
|
rs400_gart_fini(rdev);
|
|
radeon_irq_kms_fini(rdev);
|
|
radeon_fence_driver_fini(rdev);
|
|
radeon_bo_fini(rdev);
|
|
radeon_atombios_fini(rdev);
|
|
kfree(rdev->bios);
|
|
rdev->bios = NULL;
|
|
}
|
|
|
|
int rs400_init(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
/* Disable VGA */
|
|
r100_vga_render_disable(rdev);
|
|
/* Initialize scratch registers */
|
|
radeon_scratch_init(rdev);
|
|
/* Initialize surface registers */
|
|
radeon_surface_init(rdev);
|
|
/* TODO: disable VGA need to use VGA request */
|
|
/* restore some register to sane defaults */
|
|
r100_restore_sanity(rdev);
|
|
/* BIOS*/
|
|
if (!radeon_get_bios(rdev)) {
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
return -EINVAL;
|
|
}
|
|
if (rdev->is_atom_bios) {
|
|
dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
|
|
return -EINVAL;
|
|
} else {
|
|
r = radeon_combios_init(rdev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (radeon_asic_reset(rdev)) {
|
|
dev_warn(rdev->dev,
|
|
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
RREG32(R_0007C0_CP_STAT));
|
|
}
|
|
/* check if cards are posted or not */
|
|
if (radeon_boot_test_post_card(rdev) == false)
|
|
return -EINVAL;
|
|
|
|
/* Initialize clocks */
|
|
radeon_get_clock_info(rdev->ddev);
|
|
/* initialize memory controller */
|
|
rs400_mc_init(rdev);
|
|
/* Fence driver */
|
|
r = radeon_fence_driver_init(rdev);
|
|
if (r)
|
|
return r;
|
|
/* Memory manager */
|
|
r = radeon_bo_init(rdev);
|
|
if (r)
|
|
return r;
|
|
r = rs400_gart_init(rdev);
|
|
if (r)
|
|
return r;
|
|
r300_set_reg_safe(rdev);
|
|
|
|
rdev->accel_working = true;
|
|
r = rs400_startup(rdev);
|
|
if (r) {
|
|
/* Somethings want wront with the accel init stop accel */
|
|
dev_err(rdev->dev, "Disabling GPU acceleration\n");
|
|
r100_cp_fini(rdev);
|
|
radeon_wb_fini(rdev);
|
|
radeon_ib_pool_fini(rdev);
|
|
rs400_gart_fini(rdev);
|
|
radeon_irq_kms_fini(rdev);
|
|
rdev->accel_working = false;
|
|
}
|
|
return 0;
|
|
}
|