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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b4c3a8729a
At the moment all queues in a multiqueue adapter will serialise against the IOMMU table lock. This is proving to be a big issue, especially with 10Gbit ethernet. This patch creates 4 pools and tries to spread the load across them. If the table is under 1GB in size we revert back to the original behaviour of 1 pool and 1 largealloc pool. We create a hash to map CPUs to pools. Since we prefer interrupts to be affinitised to primary CPUs, without some form of hashing we are very likely to end up using the same pool. As an example, POWER7 has 4 way SMT and with 4 pools all primary threads will map to the same pool. The largealloc pool is reduced from 1/2 to 1/4 of the space to partially offset the overhead of breaking the table up into pools. Some performance numbers were obtained with a Chelsio T3 adapter on two POWER7 boxes, running a 100 session TCP round robin test. Performance improved 69% with this patch applied. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
152 lines
4.8 KiB
C
152 lines
4.8 KiB
C
/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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* Rewrite, cleanup:
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_IOMMU_H
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#define _ASM_IOMMU_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <linux/spinlock.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitops.h>
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#include <asm/machdep.h>
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#include <asm/types.h>
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#define IOMMU_PAGE_SHIFT 12
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#define IOMMU_PAGE_SIZE (ASM_CONST(1) << IOMMU_PAGE_SHIFT)
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#define IOMMU_PAGE_MASK (~((1 << IOMMU_PAGE_SHIFT) - 1))
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#define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
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/* Boot time flags */
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extern int iommu_is_off;
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extern int iommu_force_on;
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/* Pure 2^n version of get_order */
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static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
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{
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return __ilog2((size - 1) >> IOMMU_PAGE_SHIFT) + 1;
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}
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/*
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* IOMAP_MAX_ORDER defines the largest contiguous block
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* of dma space we can get. IOMAP_MAX_ORDER = 13
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* allows up to 2**12 pages (4096 * 4096) = 16 MB
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*/
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#define IOMAP_MAX_ORDER 13
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#define IOMMU_POOL_HASHBITS 2
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#define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
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struct iommu_pool {
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unsigned long start;
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unsigned long end;
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unsigned long hint;
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spinlock_t lock;
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} ____cacheline_aligned_in_smp;
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struct iommu_table {
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unsigned long it_busno; /* Bus number this table belongs to */
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unsigned long it_size; /* Size of iommu table in entries */
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unsigned long it_offset; /* Offset into global table */
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unsigned long it_base; /* mapped address of tce table */
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unsigned long it_index; /* which iommu table this is */
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unsigned long it_type; /* type: PCI or Virtual Bus */
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unsigned long it_blocksize; /* Entries in each block (cacheline) */
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unsigned long poolsize;
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unsigned long nr_pools;
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struct iommu_pool large_pool;
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struct iommu_pool pools[IOMMU_NR_POOLS];
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unsigned long *it_map; /* A simple allocation bitmap for now */
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};
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struct scatterlist;
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static inline void set_iommu_table_base(struct device *dev, void *base)
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{
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dev->archdata.dma_data.iommu_table_base = base;
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}
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static inline void *get_iommu_table_base(struct device *dev)
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{
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return dev->archdata.dma_data.iommu_table_base;
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}
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/* Frees table for an individual device node */
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extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
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/* Initializes an iommu_table based in values set in the passed-in
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* structure
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*/
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extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
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int nid);
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extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
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struct scatterlist *sglist, int nelems,
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unsigned long mask, enum dma_data_direction direction,
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struct dma_attrs *attrs);
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extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction,
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struct dma_attrs *attrs);
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extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
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size_t size, dma_addr_t *dma_handle,
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unsigned long mask, gfp_t flag, int node);
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extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
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void *vaddr, dma_addr_t dma_handle);
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extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
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struct page *page, unsigned long offset,
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size_t size, unsigned long mask,
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enum dma_data_direction direction,
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struct dma_attrs *attrs);
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extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction,
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struct dma_attrs *attrs);
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extern void iommu_init_early_pSeries(void);
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extern void iommu_init_early_dart(void);
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extern void iommu_init_early_pasemi(void);
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#ifdef CONFIG_PCI
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extern void pci_iommu_init(void);
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extern void pci_direct_iommu_init(void);
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#else
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static inline void pci_iommu_init(void) { }
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#endif
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extern void alloc_dart_table(void);
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#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
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static inline void iommu_save(void)
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{
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if (ppc_md.iommu_save)
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ppc_md.iommu_save();
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}
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static inline void iommu_restore(void)
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{
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if (ppc_md.iommu_restore)
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ppc_md.iommu_restore();
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}
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_IOMMU_H */
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