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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6523a0e155
Switch to the new the hardware port bindings. Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
990 lines
18 KiB
Plaintext
990 lines
18 KiB
Plaintext
/*
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* Hisilicon Ltd. HiP04 SoC
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*
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* Copyright (C) 2013-2014 Hisilicon Ltd.
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* Copyright (C) 2013-2014 Linaro Ltd.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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/* memory bus is 64-bit */
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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bootwrapper {
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compatible = "hisilicon,hip04-bootwrapper";
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boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU8>;
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};
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core1 {
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cpu = <&CPU9>;
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};
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core2 {
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cpu = <&CPU10>;
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};
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core3 {
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cpu = <&CPU11>;
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};
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};
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cluster3 {
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core0 {
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cpu = <&CPU12>;
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};
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core1 {
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cpu = <&CPU13>;
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};
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core2 {
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cpu = <&CPU14>;
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};
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core3 {
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cpu = <&CPU15>;
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};
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};
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};
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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CPU4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x100>;
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};
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CPU5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x101>;
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};
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CPU6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x102>;
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};
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CPU7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x103>;
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};
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CPU8: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x200>;
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};
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CPU9: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x201>;
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};
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CPU10: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x202>;
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};
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CPU11: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x203>;
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};
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CPU12: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x300>;
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};
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CPU13: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x301>;
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};
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CPU14: cpu@302 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x302>;
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};
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CPU15: cpu@303 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x303>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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clk_50m: clk_50m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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clk_168m: clk_168m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <168000000>;
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};
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clk_375m: clk_375m {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <375000000>;
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};
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soc {
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/* It's a 32-bit SoC. */
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0 0 0xe0000000 0x10000000>;
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gic: interrupt-controller@c01000 {
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compatible = "hisilicon,hip04-intc";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <1 9 0xf04>;
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reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
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<0xc04000 0x2000>, <0xc06000 0x2000>;
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};
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sysctrl: sysctrl {
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compatible = "hisilicon,sysctrl";
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reg = <0x3e00000 0x00100000>;
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};
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fabric: fabric {
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compatible = "hisilicon,hip04-fabric";
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reg = <0x302a000 0x1000>;
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};
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dual_timer0: dual_timer@3000000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x3000000 0x1000>;
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interrupts = <0 224 4>;
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clocks = <&clk_50m>, <&clk_50m>;
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clock-names = "apb_pclk";
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};
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arm-pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <0 64 4>,
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<0 65 4>,
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<0 66 4>,
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<0 67 4>,
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<0 68 4>,
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<0 69 4>,
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<0 70 4>,
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<0 71 4>,
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<0 72 4>,
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<0 73 4>,
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<0 74 4>,
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<0 75 4>,
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<0 76 4>,
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<0 77 4>,
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<0 78 4>,
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<0 79 4>;
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};
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uart0: uart@4007000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x4007000 0x1000>;
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interrupts = <0 381 4>;
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clocks = <&clk_168m>;
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clock-names = "uartclk";
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reg-shift = <2>;
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status = "disabled";
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};
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sata0: sata@a000000 {
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compatible = "hisilicon,hisi-ahci";
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reg = <0xa000000 0x1000000>;
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interrupts = <0 372 4>;
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};
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};
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etb@0,e3c42000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0xe3c42000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etb0_in_port: endpoint@0 {
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remote-endpoint = <&replicator0_out_port0>;
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};
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};
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};
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};
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etb@0,e3c82000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0xe3c82000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etb1_in_port: endpoint@0 {
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remote-endpoint = <&replicator1_out_port0>;
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};
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};
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};
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};
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etb@0,e3cc2000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0xe3cc2000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etb2_in_port: endpoint@0 {
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remote-endpoint = <&replicator2_out_port0>;
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};
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};
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};
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};
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etb@0,e3d02000 {
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compatible = "arm,coresight-etb10", "arm,primecell";
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reg = <0 0xe3d02000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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etb3_in_port: endpoint@0 {
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remote-endpoint = <&replicator3_out_port0>;
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};
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};
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};
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};
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tpiu@0,e3c05000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0 0xe3c05000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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in-ports {
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port {
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tpiu_in_port: endpoint@0 {
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remote-endpoint = <&funnel4_out_port0>;
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};
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};
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};
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};
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replicator0 {
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator0_out_port0: endpoint {
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remote-endpoint = <&etb0_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator0_out_port1: endpoint {
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remote-endpoint = <&funnel4_in_port0>;
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};
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};
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};
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in-ports {
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port {
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replicator0_in_port0: endpoint {
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remote-endpoint = <&funnel0_out_port0>;
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};
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};
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};
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};
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replicator1 {
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* replicator output ports */
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port@0 {
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reg = <0>;
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replicator1_out_port0: endpoint {
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remote-endpoint = <&etb1_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator1_out_port1: endpoint {
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remote-endpoint = <&funnel4_in_port1>;
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};
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};
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};
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in-ports {
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port {
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replicator1_in_port0: endpoint {
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remote-endpoint = <&funnel1_out_port0>;
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};
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};
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};
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};
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replicator2 {
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator2_out_port0: endpoint {
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remote-endpoint = <&etb2_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator2_out_port1: endpoint {
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remote-endpoint = <&funnel4_in_port2>;
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};
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};
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};
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in-ports {
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port {
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replicator2_in_port0: endpoint {
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remote-endpoint = <&funnel2_out_port0>;
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};
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};
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};
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};
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replicator3 {
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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out-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator3_out_port0: endpoint {
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remote-endpoint = <&etb3_in_port>;
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};
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};
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port@1 {
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reg = <1>;
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replicator3_out_port1: endpoint {
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remote-endpoint = <&funnel4_in_port3>;
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};
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};
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};
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in-ports {
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port {
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replicator3_in_port0: endpoint {
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remote-endpoint = <&funnel3_out_port0>;
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};
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};
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};
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};
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funnel@0,e3c41000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0xe3c41000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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funnel0_out_port0: endpoint {
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remote-endpoint =
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<&replicator0_in_port0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel0_in_port0: endpoint {
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remote-endpoint = <&ptm0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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funnel0_in_port1: endpoint {
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remote-endpoint = <&ptm1_out_port>;
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};
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};
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port@2 {
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reg = <2>;
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funnel0_in_port2: endpoint {
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remote-endpoint = <&ptm2_out_port>;
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};
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};
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port@3 {
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reg = <3>;
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funnel0_in_port3: endpoint {
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remote-endpoint = <&ptm3_out_port>;
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};
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};
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};
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};
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funnel@0,e3c81000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0xe3c81000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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funnel1_out_port0: endpoint {
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remote-endpoint =
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<&replicator1_in_port0>;
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};
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};
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};
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel1_in_port0: endpoint {
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remote-endpoint = <&ptm4_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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funnel1_in_port1: endpoint {
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remote-endpoint = <&ptm5_out_port>;
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};
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};
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port@2 {
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reg = <2>;
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funnel1_in_port2: endpoint {
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remote-endpoint = <&ptm6_out_port>;
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};
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};
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port@3 {
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reg = <3>;
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funnel1_in_port3: endpoint {
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remote-endpoint = <&ptm7_out_port>;
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};
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};
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};
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};
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funnel@0,e3cc1000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0xe3cc1000 0 0x1000>;
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clocks = <&clk_375m>;
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clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
funnel2_out_port0: endpoint {
|
|
remote-endpoint =
|
|
<&replicator2_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel2_in_port0: endpoint {
|
|
remote-endpoint = <&ptm8_out_port>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel2_in_port1: endpoint {
|
|
remote-endpoint = <&ptm9_out_port>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel2_in_port2: endpoint {
|
|
remote-endpoint = <&ptm10_out_port>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel2_in_port3: endpoint {
|
|
remote-endpoint = <&ptm11_out_port>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@0,e3d01000 {
|
|
compatible = "arm,coresight-funnel", "arm,primecell";
|
|
reg = <0 0xe3d01000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
funnel3_out_port0: endpoint {
|
|
remote-endpoint =
|
|
<&replicator3_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel3_in_port0: endpoint {
|
|
remote-endpoint = <&ptm12_out_port>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel3_in_port1: endpoint {
|
|
remote-endpoint = <&ptm13_out_port>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel3_in_port2: endpoint {
|
|
remote-endpoint = <&ptm14_out_port>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel3_in_port3: endpoint {
|
|
remote-endpoint = <&ptm15_out_port>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
funnel@0,e3c04000 {
|
|
compatible = "arm,coresight-funnel", "arm,primecell";
|
|
reg = <0 0xe3c04000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
out-ports {
|
|
port {
|
|
funnel4_out_port0: endpoint {
|
|
remote-endpoint = <&tpiu_in_port>;
|
|
};
|
|
};
|
|
};
|
|
|
|
in-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
funnel4_in_port0: endpoint {
|
|
remote-endpoint =
|
|
<&replicator0_out_port1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
funnel4_in_port1: endpoint {
|
|
remote-endpoint =
|
|
<&replicator1_out_port1>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
funnel4_in_port2: endpoint {
|
|
remote-endpoint =
|
|
<&replicator2_out_port1>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
funnel4_in_port3: endpoint {
|
|
remote-endpoint =
|
|
<&replicator3_out_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3c7c000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3c7c000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU0>;
|
|
out-ports {
|
|
port {
|
|
ptm0_out_port: endpoint {
|
|
remote-endpoint = <&funnel0_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3c7d000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3c7d000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU1>;
|
|
out-ports {
|
|
port {
|
|
ptm1_out_port: endpoint {
|
|
remote-endpoint = <&funnel0_in_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3c7e000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3c7e000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU2>;
|
|
out-ports {
|
|
port {
|
|
ptm2_out_port: endpoint {
|
|
remote-endpoint = <&funnel0_in_port2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3c7f000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3c7f000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU3>;
|
|
out-ports {
|
|
port {
|
|
ptm3_out_port: endpoint {
|
|
remote-endpoint = <&funnel0_in_port3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cbc000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cbc000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU4>;
|
|
out-ports {
|
|
port {
|
|
ptm4_out_port: endpoint {
|
|
remote-endpoint = <&funnel1_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cbd000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cbd000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU5>;
|
|
out-ports {
|
|
port {
|
|
ptm5_out_port: endpoint {
|
|
remote-endpoint = <&funnel1_in_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cbe000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cbe000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU6>;
|
|
out-ports {
|
|
port {
|
|
ptm6_out_port: endpoint {
|
|
remote-endpoint = <&funnel1_in_port2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cbf000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cbf000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU7>;
|
|
out-ports {
|
|
port {
|
|
ptm7_out_port: endpoint {
|
|
remote-endpoint = <&funnel1_in_port3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cfc000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cfc000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU8>;
|
|
out-ports {
|
|
port {
|
|
ptm8_out_port: endpoint {
|
|
remote-endpoint = <&funnel2_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cfd000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cfd000 0 0x1000>;
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU9>;
|
|
out-ports {
|
|
port {
|
|
ptm9_out_port: endpoint {
|
|
remote-endpoint = <&funnel2_in_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cfe000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cfe000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU10>;
|
|
out-ports {
|
|
port {
|
|
ptm10_out_port: endpoint {
|
|
remote-endpoint = <&funnel2_in_port2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3cff000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3cff000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU11>;
|
|
out-ports {
|
|
port {
|
|
ptm11_out_port: endpoint {
|
|
remote-endpoint = <&funnel2_in_port3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3d3c000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3d3c000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU12>;
|
|
out-ports {
|
|
port {
|
|
ptm12_out_port: endpoint {
|
|
remote-endpoint = <&funnel3_in_port0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3d3d000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3d3d000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU13>;
|
|
out-ports {
|
|
port {
|
|
ptm13_out_port: endpoint {
|
|
remote-endpoint = <&funnel3_in_port1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3d3e000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3d3e000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU14>;
|
|
out-ports {
|
|
port {
|
|
ptm14_out_port: endpoint {
|
|
remote-endpoint = <&funnel3_in_port2>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ptm@0,e3d3f000 {
|
|
compatible = "arm,coresight-etm3x", "arm,primecell";
|
|
reg = <0 0xe3d3f000 0 0x1000>;
|
|
|
|
clocks = <&clk_375m>;
|
|
clock-names = "apb_pclk";
|
|
cpu = <&CPU15>;
|
|
out-ports {
|
|
port {
|
|
ptm15_out_port: endpoint {
|
|
remote-endpoint = <&funnel3_in_port3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|