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The configuration address space has so far been specified in *ranges*, however it should be specified in *reg* making it a platform MEM resource. Hence used 'platform_get_resource_*' API to get configuration address space in the designware driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit Kumar <mohit.kumar@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com> Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Cc: Marek Vasut <marex@denx.de> Cc: Arnd Bergmann <arnd@arndb.de>
26 lines
952 B
Plaintext
26 lines
952 B
Plaintext
* Synopsys Designware PCIe interface
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the core.
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- reg: Should contain the configuration address space.
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- reg-names: Must be "config" for the PCIe configuration space.
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(The old way of getting the configuration address space from "ranges"
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is deprecated and should be avoided.)
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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- num-lanes: number of lanes to use
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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Optional properties:
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- reset-gpio: gpio pin number of power good signal
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