mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 14:16:37 +07:00
f15bf19b49
Modified common ColdFire PIT timer code to support the 5208 as well. It uses a different set of mask and interrupt bits than other ColdFire processors. The defines for these bits have been moved in header files and set appropriately for the different processor varients. Patch originally from Matt Waddel. Signed-off-by: Greg Ungerer <gerg@uclinux.com> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/***************************************************************************/
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/*
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* pit.c -- Motorola ColdFire PIT timer. Currently this type of
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* hardware timer only exists in the Motorola ColdFire
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* 5270/5271, 5282 and other CPUs.
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*
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* Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
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*
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*/
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/***************************************************************************/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/coldfire.h>
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#include <asm/mcfpit.h>
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#include <asm/mcfsim.h>
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/***************************************************************************/
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void coldfire_pit_tick(void)
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{
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volatile struct mcfpit *tp;
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/* Reset the ColdFire timer */
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tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
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tp->pcsr |= MCFPIT_PCSR_PIF;
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}
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/***************************************************************************/
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void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *))
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{
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volatile unsigned char *icrp;
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volatile unsigned long *imrp;
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volatile struct mcfpit *tp;
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request_irq(MCFINT_VECBASE + MCFINT_PIT1, handler, SA_INTERRUPT,
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"ColdFire Timer", NULL);
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icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
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MCFINTC_ICR0 + MCFINT_PIT1);
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*icrp = ICR_INTRCONF;
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imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
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*imrp &= ~MCFPIT_IMR_IBIT;
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/* Set up PIT timer 1 as poll clock */
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tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
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tp->pcsr = MCFPIT_PCSR_DISABLE;
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tp->pmr = ((MCF_CLK / 2) / 64) / HZ;
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tp->pcsr = MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
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MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64;
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}
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/***************************************************************************/
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unsigned long coldfire_pit_offset(void)
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{
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volatile struct mcfpit *tp;
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volatile unsigned long *ipr;
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unsigned long pmr, pcntr, offset;
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tp = (volatile struct mcfpit *) (MCF_IPSBAR + MCFPIT_BASE1);
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ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
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pmr = *(&tp->pmr);
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pcntr = *(&tp->pcntr);
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/*
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* If we are still in the first half of the upcount and a
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* timer interupt is pending, then add on a ticks worth of time.
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*/
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offset = ((pmr - pcntr) * (1000000 / HZ)) / pmr;
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if ((offset < (1000000 / HZ / 2)) && (*ipr & MCFPIT_IMR_IBIT))
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offset += 1000000 / HZ;
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return offset;
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}
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/***************************************************************************/
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