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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/* MN10300 Reset controller and watchdog timer definitions
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_RESET_REGS_H
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#define _ASM_RESET_REGS_H
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#include <asm/cpu-regs.h>
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#include <asm/exceptions.h>
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#ifdef __KERNEL__
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#ifdef CONFIG_MN10300_WD_TIMER
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#define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */
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#endif
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/*
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* watchdog timer registers
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*/
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#define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */
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#define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
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#define WDCTR_WDCK 0x07 /* clock source selection */
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#define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */
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#define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */
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#define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */
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#define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */
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#define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */
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#define WDCTR_WDRST 0x40 /* binary counter reset */
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#define WDCTR_WDCNE 0x80 /* watchdog timer enable */
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#define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
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#define RSTCTR_CHIPRST 0x01 /* chip reset */
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#define RSTCTR_DBFRST 0x02 /* double fault reset flag */
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#define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */
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#define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */
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#ifndef __ASSEMBLY__
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static inline void mn10300_proc_hard_reset(void)
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{
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RSTCTR &= ~RSTCTR_CHIPRST;
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RSTCTR |= RSTCTR_CHIPRST;
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}
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extern unsigned int watchdog_alert_counter;
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extern void watchdog_go(void);
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extern asmlinkage void watchdog_handler(void);
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extern asmlinkage
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void watchdog_interrupt(struct pt_regs *, enum exception_code);
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_RESET_REGS_H */
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