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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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62cedc4fde
R4K-style CPUs having common code to support their caches and tlb have this boolean defined by default. Allows us to remove some lines in arch/mips/mm/Makefile. Signed-off-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/3328/ Signed-off-by: John Crispin <blogic@openwrt.org>
25 lines
897 B
Makefile
25 lines
897 B
Makefile
#
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# Makefile for the Linux/MIPS-specific parts of the memory manager.
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#
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obj-y += cache.o dma-default.o extable.o fault.o \
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gup.o init.o mmap.o page.o page-funcs.o \
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tlbex.o tlbex-fault.o uasm.o
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obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
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obj-$(CONFIG_64BIT) += pgtable-64.o
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obj-$(CONFIG_HIGHMEM) += highmem.o
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obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
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obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
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obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o
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obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o tlb-r8k.o
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obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
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obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
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obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
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obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
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obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o
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obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o
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