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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c4c4594b00
Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: Chris Zankel <chris@zankel.net>
143 lines
3.1 KiB
C
143 lines
3.1 KiB
C
/*
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* arch/xtensa/mm/tlb.c
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*
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* Logic that manipulates the Xtensa MMU. Derived from MIPS.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2003 Tensilica Inc.
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*
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* Joe Taylor
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier
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*/
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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static inline void __flush_itlb_all (void)
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{
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int w, i;
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for (w = 0; w < ITLB_ARF_WAYS; w++) {
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for (i = 0; i < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); i++) {
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int e = w + (i << PAGE_SHIFT);
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invalidate_itlb_entry_no_isync(e);
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}
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}
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asm volatile ("isync\n");
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}
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static inline void __flush_dtlb_all (void)
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{
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int w, i;
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for (w = 0; w < DTLB_ARF_WAYS; w++) {
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for (i = 0; i < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); i++) {
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int e = w + (i << PAGE_SHIFT);
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invalidate_dtlb_entry_no_isync(e);
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}
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}
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asm volatile ("isync\n");
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}
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void flush_tlb_all (void)
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{
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__flush_itlb_all();
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__flush_dtlb_all();
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}
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/* If mm is current, we simply assign the current task a new ASID, thus,
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* invalidating all previous tlb entries. If mm is someone else's user mapping,
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* wie invalidate the context, thus, when that user mapping is swapped in,
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* a new context will be assigned to it.
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*/
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void flush_tlb_mm(struct mm_struct *mm)
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{
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if (mm == current->active_mm) {
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unsigned long flags;
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local_save_flags(flags);
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__get_new_mmu_context(mm);
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__load_mmu_context(mm);
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local_irq_restore(flags);
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}
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else
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mm->context = 0;
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}
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#define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2)
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#define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2)
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#if _ITLB_ENTRIES > _DTLB_ENTRIES
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# define _TLB_ENTRIES _ITLB_ENTRIES
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#else
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# define _TLB_ENTRIES _DTLB_ENTRIES
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#endif
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void flush_tlb_range (struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned long flags;
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if (mm->context == NO_CONTEXT)
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return;
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#if 0
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printk("[tlbrange<%02lx,%08lx,%08lx>]\n",
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(unsigned long)mm->context, start, end);
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#endif
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local_save_flags(flags);
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if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) {
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int oldpid = get_rasid_register();
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set_rasid_register (ASID_INSERT(mm->context));
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start &= PAGE_MASK;
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if (vma->vm_flags & VM_EXEC)
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while(start < end) {
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invalidate_itlb_mapping(start);
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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else
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while(start < end) {
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invalidate_dtlb_mapping(start);
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start += PAGE_SIZE;
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}
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set_rasid_register(oldpid);
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} else {
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flush_tlb_mm(mm);
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}
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local_irq_restore(flags);
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}
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void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
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{
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struct mm_struct* mm = vma->vm_mm;
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unsigned long flags;
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int oldpid;
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if(mm->context == NO_CONTEXT)
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return;
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local_save_flags(flags);
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oldpid = get_rasid_register();
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if (vma->vm_flags & VM_EXEC)
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invalidate_itlb_mapping(page);
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invalidate_dtlb_mapping(page);
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set_rasid_register(oldpid);
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local_irq_restore(flags);
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}
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