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f53e3c538d
DRA74x and DRA72x family of processors vary slightly in the number of CPUs. So, add different instances of PMU for each of these processor groups. Further, since the interrupts bypass crossbar and are directly connected to GIC, mark the dts nodes with relevant information. Tested with perf utility. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Lucas Weaver <l-weaver@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
48 lines
987 B
Plaintext
48 lines
987 B
Plaintext
/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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#include "dra7.dtsi"
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/ {
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compatible = "ti,dra742", "ti,dra74", "ti,dra7";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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operating-points = <
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/* kHz uV */
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1000000 1060000
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1176000 1160000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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