mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 07:56:40 +07:00
1c075f9550
There are error parameters should be corrected when calling dma_free_coherent to free rmu rx-ring buffers in fsl_open_inb_mbox() function. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
1108 lines
29 KiB
C
1108 lines
29 KiB
C
/*
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* Freescale MPC85xx/MPC86xx RapidIO RMU support
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*
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* Copyright 2009 Sysgo AG
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* Thomas Moll <thomas.moll@sysgo.com>
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* - fixed maintenance access routines, check for aligned access
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*
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* Copyright 2009 Integrated Device Technology, Inc.
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* Alex Bounine <alexandre.bounine@idt.com>
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* - Added Port-Write message handling
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* - Added Machine Check exception handling
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*
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* Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
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* Zhang Wei <wei.zhang@freescale.com>
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* Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
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* Liu Gang <Gang.Liu@freescale.com>
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*
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* Copyright 2005 MontaVista Software, Inc.
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include "fsl_rio.h"
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#define GET_RMM_HANDLE(mport) \
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(((struct rio_priv *)(mport->priv))->rmm_handle)
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/* RapidIO definition irq, which read from OF-tree */
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#define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq)
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#define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
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#define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
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#define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
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#define RIO_MIN_TX_RING_SIZE 2
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#define RIO_MAX_TX_RING_SIZE 2048
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#define RIO_MIN_RX_RING_SIZE 2
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#define RIO_MAX_RX_RING_SIZE 2048
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#define RIO_IPWMR_SEN 0x00100000
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#define RIO_IPWMR_QFIE 0x00000100
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#define RIO_IPWMR_EIE 0x00000020
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#define RIO_IPWMR_CQ 0x00000002
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#define RIO_IPWMR_PWE 0x00000001
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#define RIO_IPWSR_QF 0x00100000
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#define RIO_IPWSR_TE 0x00000080
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#define RIO_IPWSR_QFI 0x00000010
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#define RIO_IPWSR_PWD 0x00000008
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#define RIO_IPWSR_PWB 0x00000004
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#define RIO_EPWISR 0x10010
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/* EPWISR Error match value */
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#define RIO_EPWISR_PINT1 0x80000000
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#define RIO_EPWISR_PINT2 0x40000000
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#define RIO_EPWISR_MU 0x00000002
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#define RIO_EPWISR_PW 0x00000001
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#define IPWSR_CLEAR 0x98
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#define OMSR_CLEAR 0x1cb3
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#define IMSR_CLEAR 0x491
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#define IDSR_CLEAR 0x91
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#define ODSR_CLEAR 0x1c00
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#define LTLEECSR_ENABLE_ALL 0xFFC000FC
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#define RIO_LTLEECSR 0x060c
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#define RIO_IM0SR 0x64
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#define RIO_IM1SR 0x164
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#define RIO_OM0SR 0x4
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#define RIO_OM1SR 0x104
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#define RIO_DBELL_WIN_SIZE 0x1000
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#define RIO_MSG_OMR_MUI 0x00000002
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#define RIO_MSG_OSR_TE 0x00000080
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#define RIO_MSG_OSR_QOI 0x00000020
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#define RIO_MSG_OSR_QFI 0x00000010
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#define RIO_MSG_OSR_MUB 0x00000004
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#define RIO_MSG_OSR_EOMI 0x00000002
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#define RIO_MSG_OSR_QEI 0x00000001
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#define RIO_MSG_IMR_MI 0x00000002
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#define RIO_MSG_ISR_TE 0x00000080
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#define RIO_MSG_ISR_QFI 0x00000010
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#define RIO_MSG_ISR_DIQI 0x00000001
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#define RIO_MSG_DESC_SIZE 32
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#define RIO_MSG_BUFFER_SIZE 4096
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#define DOORBELL_DMR_DI 0x00000002
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#define DOORBELL_DSR_TE 0x00000080
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#define DOORBELL_DSR_QFI 0x00000010
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#define DOORBELL_DSR_DIQI 0x00000001
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#define DOORBELL_MESSAGE_SIZE 0x08
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struct rio_msg_regs {
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u32 omr;
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u32 osr;
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u32 pad1;
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u32 odqdpar;
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u32 pad2;
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u32 osar;
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u32 odpr;
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u32 odatr;
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u32 odcr;
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u32 pad3;
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u32 odqepar;
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u32 pad4[13];
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u32 imr;
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u32 isr;
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u32 pad5;
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u32 ifqdpar;
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u32 pad6;
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u32 ifqepar;
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};
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struct rio_dbell_regs {
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u32 odmr;
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u32 odsr;
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u32 pad1[4];
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u32 oddpr;
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u32 oddatr;
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u32 pad2[3];
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u32 odretcr;
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u32 pad3[12];
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u32 dmr;
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u32 dsr;
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u32 pad4;
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u32 dqdpar;
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u32 pad5;
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u32 dqepar;
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};
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struct rio_pw_regs {
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u32 pwmr;
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u32 pwsr;
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u32 epwqbar;
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u32 pwqbar;
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};
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struct rio_tx_desc {
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u32 pad1;
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u32 saddr;
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u32 dport;
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u32 dattr;
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u32 pad2;
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u32 pad3;
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u32 dwcnt;
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u32 pad4;
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};
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struct rio_msg_tx_ring {
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void *virt;
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dma_addr_t phys;
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void *virt_buffer[RIO_MAX_TX_RING_SIZE];
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dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
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int tx_slot;
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int size;
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void *dev_id;
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};
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struct rio_msg_rx_ring {
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void *virt;
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dma_addr_t phys;
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void *virt_buffer[RIO_MAX_RX_RING_SIZE];
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int rx_slot;
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int size;
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void *dev_id;
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};
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struct fsl_rmu {
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struct rio_msg_regs __iomem *msg_regs;
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struct rio_msg_tx_ring msg_tx_ring;
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struct rio_msg_rx_ring msg_rx_ring;
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int txirq;
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int rxirq;
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};
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struct rio_dbell_msg {
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u16 pad1;
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u16 tid;
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u16 sid;
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u16 info;
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};
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/**
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* fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
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* @irq: Linux interrupt number
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* @dev_instance: Pointer to interrupt-specific data
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*
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* Handles outbound message interrupts. Executes a register outbound
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* mailbox event handler and acks the interrupt occurrence.
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*/
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static irqreturn_t
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fsl_rio_tx_handler(int irq, void *dev_instance)
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{
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int osr;
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struct rio_mport *port = (struct rio_mport *)dev_instance;
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struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
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osr = in_be32(&rmu->msg_regs->osr);
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if (osr & RIO_MSG_OSR_TE) {
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pr_info("RIO: outbound message transmission error\n");
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out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE);
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goto out;
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}
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if (osr & RIO_MSG_OSR_QOI) {
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pr_info("RIO: outbound message queue overflow\n");
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out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI);
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goto out;
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}
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if (osr & RIO_MSG_OSR_EOMI) {
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u32 dqp = in_be32(&rmu->msg_regs->odqdpar);
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int slot = (dqp - rmu->msg_tx_ring.phys) >> 5;
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if (port->outb_msg[0].mcback != NULL) {
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port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id,
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-1,
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slot);
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}
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/* Ack the end-of-message interrupt */
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out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI);
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}
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out:
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return IRQ_HANDLED;
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}
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/**
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* fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
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* @irq: Linux interrupt number
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* @dev_instance: Pointer to interrupt-specific data
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*
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* Handles inbound message interrupts. Executes a registered inbound
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* mailbox event handler and acks the interrupt occurrence.
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*/
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static irqreturn_t
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fsl_rio_rx_handler(int irq, void *dev_instance)
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{
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int isr;
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struct rio_mport *port = (struct rio_mport *)dev_instance;
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struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
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isr = in_be32(&rmu->msg_regs->isr);
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if (isr & RIO_MSG_ISR_TE) {
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pr_info("RIO: inbound message reception error\n");
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out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE);
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goto out;
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}
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/* XXX Need to check/dispatch until queue empty */
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if (isr & RIO_MSG_ISR_DIQI) {
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/*
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* Can receive messages for any mailbox/letter to that
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* mailbox destination. So, make the callback with an
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* unknown/invalid mailbox number argument.
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*/
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if (port->inb_msg[0].mcback != NULL)
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port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id,
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-1,
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-1);
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/* Ack the queueing interrupt */
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out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI);
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}
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out:
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return IRQ_HANDLED;
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}
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/**
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* fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
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* @irq: Linux interrupt number
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* @dev_instance: Pointer to interrupt-specific data
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*
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* Handles doorbell interrupts. Parses a list of registered
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* doorbell event handlers and executes a matching event handler.
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*/
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static irqreturn_t
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fsl_rio_dbell_handler(int irq, void *dev_instance)
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{
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int dsr;
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struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance;
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int i;
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dsr = in_be32(&fsl_dbell->dbell_regs->dsr);
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if (dsr & DOORBELL_DSR_TE) {
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pr_info("RIO: doorbell reception error\n");
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out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE);
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goto out;
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}
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if (dsr & DOORBELL_DSR_QFI) {
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pr_info("RIO: doorbell queue full\n");
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out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI);
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}
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/* XXX Need to check/dispatch until queue empty */
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if (dsr & DOORBELL_DSR_DIQI) {
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struct rio_dbell_msg *dmsg =
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fsl_dbell->dbell_ring.virt +
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(in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
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struct rio_dbell *dbell;
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int found = 0;
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pr_debug
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("RIO: processing doorbell,"
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" sid %2.2x tid %2.2x info %4.4x\n",
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dmsg->sid, dmsg->tid, dmsg->info);
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for (i = 0; i < MAX_PORT_NUM; i++) {
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if (fsl_dbell->mport[i]) {
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list_for_each_entry(dbell,
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&fsl_dbell->mport[i]->dbells, node) {
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if ((dbell->res->start
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<= dmsg->info)
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&& (dbell->res->end
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>= dmsg->info)) {
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found = 1;
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break;
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}
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}
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if (found && dbell->dinb) {
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dbell->dinb(fsl_dbell->mport[i],
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dbell->dev_id, dmsg->sid,
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dmsg->tid,
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dmsg->info);
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break;
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}
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}
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}
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if (!found) {
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pr_debug
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("RIO: spurious doorbell,"
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" sid %2.2x tid %2.2x info %4.4x\n",
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dmsg->sid, dmsg->tid,
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dmsg->info);
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}
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setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
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out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
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}
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out:
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return IRQ_HANDLED;
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}
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void msg_unit_error_handler(void)
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{
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/*XXX: Error recovery is not implemented, we just clear errors */
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out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
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out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR);
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out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR);
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out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR);
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out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR);
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out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR);
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out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR);
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out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR);
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}
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/**
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* fsl_rio_port_write_handler - MPC85xx port write interrupt handler
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* @irq: Linux interrupt number
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* @dev_instance: Pointer to interrupt-specific data
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*
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* Handles port write interrupts. Parses a list of registered
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* port write event handlers and executes a matching event handler.
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*/
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static irqreturn_t
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fsl_rio_port_write_handler(int irq, void *dev_instance)
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{
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u32 ipwmr, ipwsr;
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struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance;
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u32 epwisr, tmp;
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epwisr = in_be32(rio_regs_win + RIO_EPWISR);
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if (!(epwisr & RIO_EPWISR_PW))
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goto pw_done;
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ipwmr = in_be32(&pw->pw_regs->pwmr);
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ipwsr = in_be32(&pw->pw_regs->pwsr);
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#ifdef DEBUG_PW
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pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
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if (ipwsr & RIO_IPWSR_QF)
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pr_debug(" QF");
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if (ipwsr & RIO_IPWSR_TE)
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pr_debug(" TE");
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if (ipwsr & RIO_IPWSR_QFI)
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pr_debug(" QFI");
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if (ipwsr & RIO_IPWSR_PWD)
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pr_debug(" PWD");
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if (ipwsr & RIO_IPWSR_PWB)
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pr_debug(" PWB");
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pr_debug(" )\n");
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#endif
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/* Schedule deferred processing if PW was received */
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if (ipwsr & RIO_IPWSR_QFI) {
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/* Save PW message (if there is room in FIFO),
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* otherwise discard it.
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*/
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if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) {
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pw->port_write_msg.msg_count++;
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kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt,
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RIO_PW_MSG_SIZE);
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} else {
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pw->port_write_msg.discard_count++;
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pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
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pw->port_write_msg.discard_count);
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}
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/* Clear interrupt and issue Clear Queue command. This allows
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* another port-write to be received.
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*/
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out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI);
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out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
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|
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schedule_work(&pw->pw_work);
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}
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|
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if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
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pw->port_write_msg.err_count++;
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pr_debug("RIO: Port-Write Transaction Err (%d)\n",
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pw->port_write_msg.err_count);
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/* Clear Transaction Error: port-write controller should be
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* disabled when clearing this error
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*/
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out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
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out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE);
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out_be32(&pw->pw_regs->pwmr, ipwmr);
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}
|
|
|
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if (ipwsr & RIO_IPWSR_PWD) {
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pw->port_write_msg.discard_count++;
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pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
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pw->port_write_msg.discard_count);
|
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out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD);
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}
|
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|
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pw_done:
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if (epwisr & RIO_EPWISR_PINT1) {
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tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
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pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
|
|
fsl_rio_port_error_handler(0);
|
|
}
|
|
|
|
if (epwisr & RIO_EPWISR_PINT2) {
|
|
tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
|
|
pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
|
|
fsl_rio_port_error_handler(1);
|
|
}
|
|
|
|
if (epwisr & RIO_EPWISR_MU) {
|
|
tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
|
|
pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
|
|
msg_unit_error_handler();
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void fsl_pw_dpc(struct work_struct *work)
|
|
{
|
|
struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work);
|
|
u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
|
|
|
|
/*
|
|
* Process port-write messages
|
|
*/
|
|
while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)msg_buffer,
|
|
RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) {
|
|
/* Process one message */
|
|
#ifdef DEBUG_PW
|
|
{
|
|
u32 i;
|
|
pr_debug("%s : Port-Write Message:", __func__);
|
|
for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
|
|
if ((i%4) == 0)
|
|
pr_debug("\n0x%02x: 0x%08x", i*4,
|
|
msg_buffer[i]);
|
|
else
|
|
pr_debug(" 0x%08x", msg_buffer[i]);
|
|
}
|
|
pr_debug("\n");
|
|
}
|
|
#endif
|
|
/* Pass the port-write message to RIO core for processing */
|
|
rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* fsl_rio_pw_enable - enable/disable port-write interface init
|
|
* @mport: Master port implementing the port write unit
|
|
* @enable: 1=enable; 0=disable port-write message handling
|
|
*/
|
|
int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
|
|
{
|
|
u32 rval;
|
|
|
|
rval = in_be32(&pw->pw_regs->pwmr);
|
|
|
|
if (enable)
|
|
rval |= RIO_IPWMR_PWE;
|
|
else
|
|
rval &= ~RIO_IPWMR_PWE;
|
|
|
|
out_be32(&pw->pw_regs->pwmr, rval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* fsl_rio_port_write_init - MPC85xx port write interface init
|
|
* @mport: Master port implementing the port write unit
|
|
*
|
|
* Initializes port write unit hardware and DMA buffer
|
|
* ring. Called from fsl_rio_setup(). Returns %0 on success
|
|
* or %-ENOMEM on failure.
|
|
*/
|
|
|
|
int fsl_rio_port_write_init(struct fsl_rio_pw *pw)
|
|
{
|
|
int rc = 0;
|
|
|
|
/* Following configurations require a disabled port write controller */
|
|
out_be32(&pw->pw_regs->pwmr,
|
|
in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE);
|
|
|
|
/* Initialize port write */
|
|
pw->port_write_msg.virt = dma_alloc_coherent(pw->dev,
|
|
RIO_PW_MSG_SIZE,
|
|
&pw->port_write_msg.phys, GFP_KERNEL);
|
|
if (!pw->port_write_msg.virt) {
|
|
pr_err("RIO: unable allocate port write queue\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pw->port_write_msg.err_count = 0;
|
|
pw->port_write_msg.discard_count = 0;
|
|
|
|
/* Point dequeue/enqueue pointers at first entry */
|
|
out_be32(&pw->pw_regs->epwqbar, 0);
|
|
out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys);
|
|
|
|
pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
|
|
in_be32(&pw->pw_regs->epwqbar),
|
|
in_be32(&pw->pw_regs->pwqbar));
|
|
|
|
/* Clear interrupt status IPWSR */
|
|
out_be32(&pw->pw_regs->pwsr,
|
|
(RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
|
|
|
|
/* Configure port write contoller for snooping enable all reporting,
|
|
clear queue full */
|
|
out_be32(&pw->pw_regs->pwmr,
|
|
RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
|
|
|
|
|
|
/* Hook up port-write handler */
|
|
rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler,
|
|
IRQF_SHARED, "port-write", (void *)pw);
|
|
if (rc < 0) {
|
|
pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
|
|
goto err_out;
|
|
}
|
|
/* Enable Error Interrupt */
|
|
out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
|
|
|
|
INIT_WORK(&pw->pw_work, fsl_pw_dpc);
|
|
spin_lock_init(&pw->pw_fifo_lock);
|
|
if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
|
|
pr_err("FIFO allocation failed\n");
|
|
rc = -ENOMEM;
|
|
goto err_out_irq;
|
|
}
|
|
|
|
pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
|
|
in_be32(&pw->pw_regs->pwmr),
|
|
in_be32(&pw->pw_regs->pwsr));
|
|
|
|
return rc;
|
|
|
|
err_out_irq:
|
|
free_irq(IRQ_RIO_PW(pw), (void *)pw);
|
|
err_out:
|
|
dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE,
|
|
pw->port_write_msg.virt,
|
|
pw->port_write_msg.phys);
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* fsl_rio_doorbell_send - Send a MPC85xx doorbell message
|
|
* @mport: RapidIO master port info
|
|
* @index: ID of RapidIO interface
|
|
* @destid: Destination ID of target device
|
|
* @data: 16-bit info field of RapidIO doorbell message
|
|
*
|
|
* Sends a MPC85xx doorbell message. Returns %0 on success or
|
|
* %-EINVAL on failure.
|
|
*/
|
|
int fsl_rio_doorbell_send(struct rio_mport *mport,
|
|
int index, u16 destid, u16 data)
|
|
{
|
|
pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
|
|
index, destid, data);
|
|
|
|
/* In the serial version silicons, such as MPC8548, MPC8641,
|
|
* below operations is must be.
|
|
*/
|
|
out_be32(&dbell->dbell_regs->odmr, 0x00000000);
|
|
out_be32(&dbell->dbell_regs->odretcr, 0x00000004);
|
|
out_be32(&dbell->dbell_regs->oddpr, destid << 16);
|
|
out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
|
|
out_be32(&dbell->dbell_regs->odmr, 0x00000001);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* fsl_add_outb_message - Add message to the MPC85xx outbound message queue
|
|
* @mport: Master port with outbound message queue
|
|
* @rdev: Target of outbound message
|
|
* @mbox: Outbound mailbox
|
|
* @buffer: Message to add to outbound queue
|
|
* @len: Length of message
|
|
*
|
|
* Adds the @buffer message to the MPC85xx outbound message queue. Returns
|
|
* %0 on success or %-EINVAL on failure.
|
|
*/
|
|
int
|
|
fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
|
|
void *buffer, size_t len)
|
|
{
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
u32 omr;
|
|
struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt
|
|
+ rmu->msg_tx_ring.tx_slot;
|
|
int ret = 0;
|
|
|
|
pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
|
|
"%p len %8.8zx\n", rdev->destid, mbox, buffer, len);
|
|
if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* Copy and clear rest of buffer */
|
|
memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer,
|
|
len);
|
|
if (len < (RIO_MAX_MSG_SIZE - 4))
|
|
memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot]
|
|
+ len, 0, RIO_MAX_MSG_SIZE - len);
|
|
|
|
/* Set mbox field for message, and set destid */
|
|
desc->dport = (rdev->destid << 16) | (mbox & 0x3);
|
|
|
|
/* Enable EOMI interrupt and priority */
|
|
desc->dattr = 0x28000000 | ((mport->index) << 20);
|
|
|
|
/* Set transfer size aligned to next power of 2 (in double words) */
|
|
desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
|
|
|
|
/* Set snooping and source buffer address */
|
|
desc->saddr = 0x00000004
|
|
| rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot];
|
|
|
|
/* Increment enqueue pointer */
|
|
omr = in_be32(&rmu->msg_regs->omr);
|
|
out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
|
|
|
|
/* Go to next descriptor */
|
|
if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size)
|
|
rmu->msg_tx_ring.tx_slot = 0;
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
|
|
* @mport: Master port implementing the outbound message unit
|
|
* @dev_id: Device specific pointer to pass on event
|
|
* @mbox: Mailbox to open
|
|
* @entries: Number of entries in the outbound mailbox ring
|
|
*
|
|
* Initializes buffer ring, request the outbound message interrupt,
|
|
* and enables the outbound message unit. Returns %0 on success and
|
|
* %-EINVAL or %-ENOMEM on failure.
|
|
*/
|
|
int
|
|
fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
|
|
{
|
|
int i, j, rc = 0;
|
|
struct rio_priv *priv = mport->priv;
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
|
|
if ((entries < RIO_MIN_TX_RING_SIZE) ||
|
|
(entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
|
|
rc = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* Initialize shadow copy ring */
|
|
rmu->msg_tx_ring.dev_id = dev_id;
|
|
rmu->msg_tx_ring.size = entries;
|
|
|
|
for (i = 0; i < rmu->msg_tx_ring.size; i++) {
|
|
rmu->msg_tx_ring.virt_buffer[i] =
|
|
dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
|
|
&rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
|
|
if (!rmu->msg_tx_ring.virt_buffer[i]) {
|
|
rc = -ENOMEM;
|
|
for (j = 0; j < rmu->msg_tx_ring.size; j++)
|
|
if (rmu->msg_tx_ring.virt_buffer[j])
|
|
dma_free_coherent(priv->dev,
|
|
RIO_MSG_BUFFER_SIZE,
|
|
rmu->msg_tx_ring.
|
|
virt_buffer[j],
|
|
rmu->msg_tx_ring.
|
|
phys_buffer[j]);
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
/* Initialize outbound message descriptor ring */
|
|
rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
|
|
rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
|
|
&rmu->msg_tx_ring.phys, GFP_KERNEL);
|
|
if (!rmu->msg_tx_ring.virt) {
|
|
rc = -ENOMEM;
|
|
goto out_dma;
|
|
}
|
|
memset(rmu->msg_tx_ring.virt, 0,
|
|
rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
|
|
rmu->msg_tx_ring.tx_slot = 0;
|
|
|
|
/* Point dequeue/enqueue pointers at first entry in ring */
|
|
out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys);
|
|
out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys);
|
|
|
|
/* Configure for snooping */
|
|
out_be32(&rmu->msg_regs->osar, 0x00000004);
|
|
|
|
/* Clear interrupt status */
|
|
out_be32(&rmu->msg_regs->osr, 0x000000b3);
|
|
|
|
/* Hook up outbound message handler */
|
|
rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
|
|
"msg_tx", (void *)mport);
|
|
if (rc < 0)
|
|
goto out_irq;
|
|
|
|
/*
|
|
* Configure outbound message unit
|
|
* Snooping
|
|
* Interrupts (all enabled, except QEIE)
|
|
* Chaining mode
|
|
* Disable
|
|
*/
|
|
out_be32(&rmu->msg_regs->omr, 0x00100220);
|
|
|
|
/* Set number of entries */
|
|
out_be32(&rmu->msg_regs->omr,
|
|
in_be32(&rmu->msg_regs->omr) |
|
|
((get_bitmask_order(entries) - 2) << 12));
|
|
|
|
/* Now enable the unit */
|
|
out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1);
|
|
|
|
out:
|
|
return rc;
|
|
|
|
out_irq:
|
|
dma_free_coherent(priv->dev,
|
|
rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
|
|
rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
|
|
|
|
out_dma:
|
|
for (i = 0; i < rmu->msg_tx_ring.size; i++)
|
|
dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
|
|
rmu->msg_tx_ring.virt_buffer[i],
|
|
rmu->msg_tx_ring.phys_buffer[i]);
|
|
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
|
|
* @mport: Master port implementing the outbound message unit
|
|
* @mbox: Mailbox to close
|
|
*
|
|
* Disables the outbound message unit, free all buffers, and
|
|
* frees the outbound message interrupt.
|
|
*/
|
|
void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
|
|
{
|
|
struct rio_priv *priv = mport->priv;
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
|
|
/* Disable inbound message unit */
|
|
out_be32(&rmu->msg_regs->omr, 0);
|
|
|
|
/* Free ring */
|
|
dma_free_coherent(priv->dev,
|
|
rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
|
|
rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
|
|
|
|
/* Free interrupt */
|
|
free_irq(IRQ_RIO_TX(mport), (void *)mport);
|
|
}
|
|
|
|
/**
|
|
* fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
|
|
* @mport: Master port implementing the inbound message unit
|
|
* @dev_id: Device specific pointer to pass on event
|
|
* @mbox: Mailbox to open
|
|
* @entries: Number of entries in the inbound mailbox ring
|
|
*
|
|
* Initializes buffer ring, request the inbound message interrupt,
|
|
* and enables the inbound message unit. Returns %0 on success
|
|
* and %-EINVAL or %-ENOMEM on failure.
|
|
*/
|
|
int
|
|
fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
|
|
{
|
|
int i, rc = 0;
|
|
struct rio_priv *priv = mport->priv;
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
|
|
if ((entries < RIO_MIN_RX_RING_SIZE) ||
|
|
(entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
|
|
rc = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* Initialize client buffer ring */
|
|
rmu->msg_rx_ring.dev_id = dev_id;
|
|
rmu->msg_rx_ring.size = entries;
|
|
rmu->msg_rx_ring.rx_slot = 0;
|
|
for (i = 0; i < rmu->msg_rx_ring.size; i++)
|
|
rmu->msg_rx_ring.virt_buffer[i] = NULL;
|
|
|
|
/* Initialize inbound message ring */
|
|
rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
|
|
rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
|
|
&rmu->msg_rx_ring.phys, GFP_KERNEL);
|
|
if (!rmu->msg_rx_ring.virt) {
|
|
rc = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
/* Point dequeue/enqueue pointers at first entry in ring */
|
|
out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys);
|
|
out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys);
|
|
|
|
/* Clear interrupt status */
|
|
out_be32(&rmu->msg_regs->isr, 0x00000091);
|
|
|
|
/* Hook up inbound message handler */
|
|
rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
|
|
"msg_rx", (void *)mport);
|
|
if (rc < 0) {
|
|
dma_free_coherent(priv->dev,
|
|
rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
|
|
rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Configure inbound message unit:
|
|
* Snooping
|
|
* 4KB max message size
|
|
* Unmask all interrupt sources
|
|
* Disable
|
|
*/
|
|
out_be32(&rmu->msg_regs->imr, 0x001b0060);
|
|
|
|
/* Set number of queue entries */
|
|
setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
|
|
|
|
/* Now enable the unit */
|
|
setbits32(&rmu->msg_regs->imr, 0x1);
|
|
|
|
out:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
|
|
* @mport: Master port implementing the inbound message unit
|
|
* @mbox: Mailbox to close
|
|
*
|
|
* Disables the inbound message unit, free all buffers, and
|
|
* frees the inbound message interrupt.
|
|
*/
|
|
void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
|
|
{
|
|
struct rio_priv *priv = mport->priv;
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
|
|
/* Disable inbound message unit */
|
|
out_be32(&rmu->msg_regs->imr, 0);
|
|
|
|
/* Free ring */
|
|
dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
|
|
rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
|
|
|
|
/* Free interrupt */
|
|
free_irq(IRQ_RIO_RX(mport), (void *)mport);
|
|
}
|
|
|
|
/**
|
|
* fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
|
|
* @mport: Master port implementing the inbound message unit
|
|
* @mbox: Inbound mailbox number
|
|
* @buf: Buffer to add to inbound queue
|
|
*
|
|
* Adds the @buf buffer to the MPC85xx inbound message queue. Returns
|
|
* %0 on success or %-EINVAL on failure.
|
|
*/
|
|
int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
|
|
{
|
|
int rc = 0;
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
|
|
pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
|
|
rmu->msg_rx_ring.rx_slot);
|
|
|
|
if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) {
|
|
printk(KERN_ERR
|
|
"RIO: error adding inbound buffer %d, buffer exists\n",
|
|
rmu->msg_rx_ring.rx_slot);
|
|
rc = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf;
|
|
if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size)
|
|
rmu->msg_rx_ring.rx_slot = 0;
|
|
|
|
out:
|
|
return rc;
|
|
}
|
|
|
|
/**
|
|
* fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
|
|
* @mport: Master port implementing the inbound message unit
|
|
* @mbox: Inbound mailbox number
|
|
*
|
|
* Gets the next available inbound message from the inbound message queue.
|
|
* A pointer to the message is returned on success or NULL on failure.
|
|
*/
|
|
void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
|
|
{
|
|
struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
|
|
u32 phys_buf;
|
|
void *virt_buf;
|
|
void *buf = NULL;
|
|
int buf_idx;
|
|
|
|
phys_buf = in_be32(&rmu->msg_regs->ifqdpar);
|
|
|
|
/* If no more messages, then bail out */
|
|
if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
|
|
goto out2;
|
|
|
|
virt_buf = rmu->msg_rx_ring.virt + (phys_buf
|
|
- rmu->msg_rx_ring.phys);
|
|
buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
|
|
buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
|
|
|
|
if (!buf) {
|
|
printk(KERN_ERR
|
|
"RIO: inbound message copy failed, no buffers\n");
|
|
goto out1;
|
|
}
|
|
|
|
/* Copy max message size, caller is expected to allocate that big */
|
|
memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE);
|
|
|
|
/* Clear the available buffer */
|
|
rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
|
|
|
|
out1:
|
|
setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
|
|
|
|
out2:
|
|
return buf;
|
|
}
|
|
|
|
/**
|
|
* fsl_rio_doorbell_init - MPC85xx doorbell interface init
|
|
* @mport: Master port implementing the inbound doorbell unit
|
|
*
|
|
* Initializes doorbell unit hardware and inbound DMA buffer
|
|
* ring. Called from fsl_rio_setup(). Returns %0 on success
|
|
* or %-ENOMEM on failure.
|
|
*/
|
|
int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell)
|
|
{
|
|
int rc = 0;
|
|
|
|
/* Initialize inbound doorbells */
|
|
dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 *
|
|
DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL);
|
|
if (!dbell->dbell_ring.virt) {
|
|
printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
|
|
rc = -ENOMEM;
|
|
goto out;
|
|
}
|
|
|
|
/* Point dequeue/enqueue pointers at first entry in ring */
|
|
out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys);
|
|
out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys);
|
|
|
|
/* Clear interrupt status */
|
|
out_be32(&dbell->dbell_regs->dsr, 0x00000091);
|
|
|
|
/* Hook up doorbell handler */
|
|
rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0,
|
|
"dbell_rx", (void *)dbell);
|
|
if (rc < 0) {
|
|
dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE,
|
|
dbell->dbell_ring.virt, dbell->dbell_ring.phys);
|
|
printk(KERN_ERR
|
|
"MPC85xx RIO: unable to request inbound doorbell irq");
|
|
goto out;
|
|
}
|
|
|
|
/* Configure doorbells for snooping, 512 entries, and enable */
|
|
out_be32(&dbell->dbell_regs->dmr, 0x00108161);
|
|
|
|
out:
|
|
return rc;
|
|
}
|
|
|
|
int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node)
|
|
{
|
|
struct rio_priv *priv;
|
|
struct fsl_rmu *rmu;
|
|
u64 msg_start;
|
|
const u32 *msg_addr;
|
|
int mlen;
|
|
int aw;
|
|
|
|
if (!mport || !mport->priv)
|
|
return -EINVAL;
|
|
|
|
priv = mport->priv;
|
|
|
|
if (!node) {
|
|
dev_warn(priv->dev, "Can't get %s property 'fsl,rmu'\n",
|
|
priv->dev->of_node->full_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL);
|
|
if (!rmu)
|
|
return -ENOMEM;
|
|
|
|
aw = of_n_addr_cells(node);
|
|
msg_addr = of_get_property(node, "reg", &mlen);
|
|
if (!msg_addr) {
|
|
pr_err("%s: unable to find 'reg' property of message-unit\n",
|
|
node->full_name);
|
|
kfree(rmu);
|
|
return -ENOMEM;
|
|
}
|
|
msg_start = of_read_number(msg_addr, aw);
|
|
|
|
rmu->msg_regs = (struct rio_msg_regs *)
|
|
(rmu_regs_win + (u32)msg_start);
|
|
|
|
rmu->txirq = irq_of_parse_and_map(node, 0);
|
|
rmu->rxirq = irq_of_parse_and_map(node, 1);
|
|
printk(KERN_INFO "%s: txirq: %d, rxirq %d\n",
|
|
node->full_name, rmu->txirq, rmu->rxirq);
|
|
|
|
priv->rmm_handle = rmu;
|
|
|
|
rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
|
|
rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
|
|
rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
|
|
|
|
return 0;
|
|
}
|