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f109674951
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010, i.e. AXI3 Cacheable bit set. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Signed-off-by: Horia Geant? <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
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| .. | ||
| caamalg.c | ||
| caamhash.c | ||
| caamrng.c | ||
| compat.h | ||
| ctrl.c | ||
| ctrl.h | ||
| desc_constr.h | ||
| desc.h | ||
| error.c | ||
| error.h | ||
| intern.h | ||
| jr.c | ||
| jr.h | ||
| Kconfig | ||
| key_gen.c | ||
| key_gen.h | ||
| Makefile | ||
| pdb.h | ||
| regs.h | ||
| sg_sw_sec4.h | ||