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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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512b2203e4
Do the real sync by using mbar instruction. Signed-off-by: Stefan Asserhall <stefan.asserhall@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
67 lines
1.4 KiB
ArmAsm
67 lines
1.4 KiB
ArmAsm
/*
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* Miscellaneous low-level MMU functions.
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*
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* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008-2009 PetaLogix
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* Copyright (C) 2007 Xilinx, Inc. All rights reserved.
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*
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* Derived from arch/ppc/kernel/misc.S
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#include <linux/linkage.h>
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <linux/errno.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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.text
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/*
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* Flush MMU TLB
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*
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* We avoid flushing the pinned 0, 1 and possibly 2 entries.
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*/
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.globl _tlbia;
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.type _tlbia, @function
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.align 4;
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_tlbia:
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lwi r12, r0, tlb_skip;
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/* isync */
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_tlbia_1:
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mts rtlbx, r12
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nop
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mts rtlbhi, r0 /* flush: ensure V is clear */
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nop
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rsubi r11, r12, MICROBLAZE_TLB_SIZE - 1
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bneid r11, _tlbia_1 /* loop for all entries */
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addik r12, r12, 1
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mbar 1 /* sync */
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rtsd r15, 8
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nop
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.size _tlbia, . - _tlbia
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/*
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* Flush MMU TLB for a particular address (in r5)
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*/
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.globl _tlbie;
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.type _tlbie, @function
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.align 4;
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_tlbie:
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mts rtlbsx, r5 /* look up the address in TLB */
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nop
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mfs r12, rtlbx /* Retrieve index */
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nop
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blti r12, _tlbie_1 /* Check if found */
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mts rtlbhi, r0 /* flush: ensure V is clear */
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nop
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mbar 1 /* sync */
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_tlbie_1:
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rtsd r15, 8
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nop
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.size _tlbie, . - _tlbie
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