mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 01:45:23 +07:00
4305f42401
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS for 4.8. Also includes is a
minor SSB cleanup as SSB code traditionally is merged through the MIPS
tree:
ATH25:
- MIPS: Add default configuration for ath25
Boot:
- For zboot, copy appended dtb to the end of the kernel
- store the appended dtb address in a variable
BPF:
- Fix off by one error in offset allocation
Cobalt code:
- Fix typos
Core code:
- debugfs_create_file returns NULL on error, so don't use IS_ERR for
testing for errors.
- Fix double locking issue in RM7000 S-cache code. This would only
affect RM7000 ARC systems on reboot.
- Fix page table corruption on THP permission changes.
- Use compat_sys_keyctl for 32 bit userspace on 64 bit kernels.
David says, there are no compatibility issues raised by this fix.
- Move some signal code around.
- Rewrite r4k count/compare clockevent device registration such that
min_delta_ticks/max_delta_ticks files are guaranteed to be
initialized.
- Only register r4k count/compare as clockevent device if we can
assume the clock to be constant.
- Fix MSA asm warnings in control reg accessors
- uasm and tlbex fixes and tweaking.
- Print segment physical address when EU=1.
- Define AT_VECTOR_SIZE_ARCH for ARCH_DLINFO.
- CP: Allow booting by VP other than VP 0
- Cache handling fixes and optimizations for r4k class caches
- Add hotplug support for R6 processors
- Cleanup hotplug bits in kconfig
- traps: return correct si code for accessing nonmapped addresses
- Remove cpu_has_safe_index_cacheops
Lantiq:
- Register IRQ handler for virtual IRQ number
- Fix EIU interrupt loading code
- Use the real EXIN count
- Fix build error.
Loongson 3:
- Increase HPET_MIN_PROG_DELTA and decrease HPET_MIN_CYCLES
Octeon:
- Delete built-in DTB pruning code for D-Link DSR-1000N.
- Clean up GPIO definitions in dlink_dsr-1000n.dts.
- Add more LEDs to the DSR-100n DTS
- Fix off by one in octeon_irq_gpio_map()
- Typo fixes
- Enable SATA by default in cavium_octeon_defconfig
- Support readq/writeq()
- Remove forced mappings of USB interrupts.
- Ensure DMA descriptors are always in the low 4GB
- Improve USB reset code for OCTEON II.
Pistachio:
- Add maintainers entry for pistachio SoC Support
- Remove plat_setup_iocoherency
Ralink:
- Fix pwm UART in spis group pinmux.
SSB:
- Change bare unsigned to unsigned int to suit coding style
Tools:
- Fix reloc tool compiler warnings.
Other:
- Delete use of ARCH_WANT_OPTIONAL_GPIOLIB"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (61 commits)
MIPS: mm: Fix definition of R6 cache instruction
MIPS: tools: Fix relocs tool compiler warnings
MIPS: Cobalt: Fix typo
MIPS: Octeon: Fix typo
MIPS: Lantiq: Fix build failure
MIPS: Use CPHYSADDR to implement mips32 __pa
MIPS: Octeon: Dlink_dsr-1000n.dts: add more leds.
MIPS: Octeon: Clean up GPIO definitions in dlink_dsr-1000n.dts.
MIPS: Octeon: Delete built-in DTB pruning code for D-Link DSR-1000N.
MIPS: store the appended dtb address in a variable
MIPS: ZBOOT: copy appended dtb to the end of the kernel
MIPS: ralink: fix spis group pinmux
MIPS: Factor o32 specific code into signal_o32.c
MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is present
MIPS: Use per-mm page to execute branch delay slot instructions
MIPS: Modify error handling
MIPS: c-r4k: Use SMP calls for CM indexed cache ops
MIPS: c-r4k: Avoid small flush_icache_range SMP calls
MIPS: c-r4k: Local flush_icache_range cache op override
MIPS: c-r4k: Split r4k_flush_kernel_vmap_range()
...
136 lines
2.7 KiB
C
136 lines
2.7 KiB
C
/*
|
|
* Pistachio platform setup
|
|
*
|
|
* Copyright (C) 2014 Google, Inc.
|
|
* Copyright (C) 2016 Imagination Technologies
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/of_address.h>
|
|
#include <linux/of_fdt.h>
|
|
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/dma-coherence.h>
|
|
#include <asm/fw/fw.h>
|
|
#include <asm/mips-boards/generic.h>
|
|
#include <asm/mips-cm.h>
|
|
#include <asm/mips-cpc.h>
|
|
#include <asm/prom.h>
|
|
#include <asm/smp-ops.h>
|
|
#include <asm/traps.h>
|
|
|
|
/*
|
|
* Core revision register decoding
|
|
* Bits 23 to 20: Major rev
|
|
* Bits 15 to 8: Minor rev
|
|
* Bits 7 to 0: Maintenance rev
|
|
*/
|
|
#define PISTACHIO_CORE_REV_REG 0xB81483D0
|
|
#define PISTACHIO_CORE_REV_A1 0x00100006
|
|
#define PISTACHIO_CORE_REV_B0 0x00100106
|
|
|
|
const char *get_system_type(void)
|
|
{
|
|
u32 core_rev;
|
|
const char *sys_type;
|
|
|
|
core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG);
|
|
|
|
switch (core_rev) {
|
|
case PISTACHIO_CORE_REV_B0:
|
|
sys_type = "IMG Pistachio SoC (B0)";
|
|
break;
|
|
|
|
case PISTACHIO_CORE_REV_A1:
|
|
sys_type = "IMG Pistachio SoC (A1)";
|
|
break;
|
|
|
|
default:
|
|
sys_type = "IMG Pistachio SoC";
|
|
break;
|
|
}
|
|
|
|
return sys_type;
|
|
}
|
|
|
|
void __init *plat_get_fdt(void)
|
|
{
|
|
if (fw_arg0 != -2)
|
|
panic("Device-tree not present");
|
|
return (void *)fw_arg1;
|
|
}
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
__dt_setup_arch(plat_get_fdt());
|
|
}
|
|
|
|
#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
|
|
#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
|
|
|
|
phys_addr_t mips_cpc_default_phys_base(void)
|
|
{
|
|
return DEFAULT_CPC_BASE_ADDR;
|
|
}
|
|
|
|
phys_addr_t mips_cdmm_phys_base(void)
|
|
{
|
|
return DEFAULT_CDMM_BASE_ADDR;
|
|
}
|
|
|
|
static void __init mips_nmi_setup(void)
|
|
{
|
|
void *base;
|
|
extern char except_vec_nmi;
|
|
|
|
base = cpu_has_veic ?
|
|
(void *)(CAC_BASE + 0xa80) :
|
|
(void *)(CAC_BASE + 0x380);
|
|
memcpy(base, &except_vec_nmi, 0x80);
|
|
flush_icache_range((unsigned long)base,
|
|
(unsigned long)base + 0x80);
|
|
}
|
|
|
|
static void __init mips_ejtag_setup(void)
|
|
{
|
|
void *base;
|
|
extern char except_vec_ejtag_debug;
|
|
|
|
base = cpu_has_veic ?
|
|
(void *)(CAC_BASE + 0xa00) :
|
|
(void *)(CAC_BASE + 0x300);
|
|
memcpy(base, &except_vec_ejtag_debug, 0x80);
|
|
flush_icache_range((unsigned long)base,
|
|
(unsigned long)base + 0x80);
|
|
}
|
|
|
|
void __init prom_init(void)
|
|
{
|
|
board_nmi_handler_setup = mips_nmi_setup;
|
|
board_ejtag_handler_setup = mips_ejtag_setup;
|
|
|
|
mips_cm_probe();
|
|
mips_cpc_probe();
|
|
register_cps_smp_ops();
|
|
|
|
pr_info("SoC Type: %s\n", get_system_type());
|
|
}
|
|
|
|
void __init prom_free_prom_memory(void)
|
|
{
|
|
}
|
|
|
|
void __init device_tree_init(void)
|
|
{
|
|
if (!initial_boot_params)
|
|
return;
|
|
|
|
unflatten_and_copy_device_tree();
|
|
}
|