linux_dsm_epyc7002/arch
Marc Orr f0b5105af6 kvm: nvmx: limit atomic switch MSRs
Allowing an unlimited number of MSRs to be specified via the VMX
load/store MSR lists (e.g., vm-entry MSR load list) is bad for two
reasons. First, a guest can specify an unreasonable number of MSRs,
forcing KVM to process all of them in software. Second, the SDM bounds
the number of MSRs allowed to be packed into the atomic switch MSR lists.
Quoting the "Miscellaneous Data" section in the "VMX Capability
Reporting Facility" appendix:

"Bits 27:25 is used to compute the recommended maximum number of MSRs
that should appear in the VM-exit MSR-store list, the VM-exit MSR-load
list, or the VM-entry MSR-load list. Specifically, if the value bits
27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the recommended
maximum number of MSRs to be included in each list. If the limit is
exceeded, undefined processor behavior may result (including a machine
check during the VMX transition)."

Because KVM needs to protect itself and can't model "undefined processor
behavior", arbitrarily force a VM-entry to fail due to MSR loading when
the MSR load list is too large. Similarly, trigger an abort during a VM
exit that encounters an MSR load list or MSR store list that is too large.

The MSR list size is intentionally not pre-checked so as to maintain
compatibility with hardware inasmuch as possible.

Test these new checks with the kvm-unit-test "x86: nvmx: test max atomic
switch MSRs".

Suggested-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Peter Shier <pshier@google.com>
Signed-off-by: Marc Orr <marcorr@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-24 16:32:15 +02:00
..
alpha Kbuild updates for v5.4 2019-09-20 08:36:47 -07:00
arc Kbuild updates for v5.4 2019-09-20 08:36:47 -07:00
arm pci-v5.4-changes 2019-09-23 19:16:01 -07:00
arm64 pci-v5.4-changes 2019-09-23 19:16:01 -07:00
c6x dma-mapping: remove CONFIG_ARCH_NO_COHERENT_DMA_MMAP 2019-09-04 11:13:18 +02:00
csky hmm related patches for 5.4 2019-09-21 10:07:42 -07:00
h8300 h8300 update for 5.3 2019-07-17 09:36:38 -07:00
hexagon hexagon: switch to generic version of pte allocation 2019-07-21 09:53:00 -07:00
ia64 Kbuild updates for v5.4 2019-09-20 08:36:47 -07:00
m68k Modules updates for v5.4 2019-09-22 10:34:46 -07:00
microblaze pci-v5.4-changes 2019-09-23 19:16:01 -07:00
mips pci-v5.4-changes 2019-09-23 19:16:01 -07:00
nds32 dma-mapping updates for 5.4: 2019-09-19 13:27:23 -07:00
nios2 nios2 update for v5.3-rc1 2019-07-12 15:38:05 -07:00
openrisc hmm related patches for 5.4 2019-09-21 10:07:42 -07:00
parisc Kbuild updates for v5.4 2019-09-20 08:36:47 -07:00
powerpc pci-v5.4-changes 2019-09-23 19:16:01 -07:00
riscv Kbuild updates for v5.4 2019-09-20 08:36:47 -07:00
s390 hmm related patches for 5.4 2019-09-21 10:07:42 -07:00
sh dma-mapping updates for 5.4: 2019-09-19 13:27:23 -07:00
sparc pci-v5.4-changes 2019-09-23 19:16:01 -07:00
um This pull request contains the following changes for UML: 2019-09-21 11:07:02 -07:00
unicore32 dma-mapping updates for 5.4: 2019-09-19 13:27:23 -07:00
x86 kvm: nvmx: limit atomic switch MSRs 2019-09-24 16:32:15 +02:00
xtensa dma-mapping updates for 5.4: 2019-09-19 13:27:23 -07:00
.gitignore
Kconfig powerpc updates for 5.4 2019-09-20 11:48:06 -07:00