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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3a2baff783
The DMA API is preferred; no functional change. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Roland Dreier <rolandd@cisco.com>
345 lines
8.9 KiB
C
345 lines
8.9 KiB
C
/*
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* Copyright (c) 2004 Topspin Communications. All rights reserved.
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* Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MTHCA_PROVIDER_H
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#define MTHCA_PROVIDER_H
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#include <rdma/ib_verbs.h>
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#include <rdma/ib_pack.h>
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#define MTHCA_MPT_FLAG_ATOMIC (1 << 14)
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#define MTHCA_MPT_FLAG_REMOTE_WRITE (1 << 13)
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#define MTHCA_MPT_FLAG_REMOTE_READ (1 << 12)
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#define MTHCA_MPT_FLAG_LOCAL_WRITE (1 << 11)
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#define MTHCA_MPT_FLAG_LOCAL_READ (1 << 10)
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struct mthca_buf_list {
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void *buf;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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};
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union mthca_buf {
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struct mthca_buf_list direct;
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struct mthca_buf_list *page_list;
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};
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struct mthca_uar {
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unsigned long pfn;
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int index;
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};
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struct mthca_user_db_table;
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struct mthca_ucontext {
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struct ib_ucontext ibucontext;
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struct mthca_uar uar;
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struct mthca_user_db_table *db_tab;
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int reg_mr_warned;
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};
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struct mthca_mtt;
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struct mthca_mr {
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struct ib_mr ibmr;
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struct ib_umem *umem;
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struct mthca_mtt *mtt;
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};
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struct mthca_fmr {
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struct ib_fmr ibmr;
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struct ib_fmr_attr attr;
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struct mthca_mtt *mtt;
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int maps;
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union {
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struct {
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struct mthca_mpt_entry __iomem *mpt;
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u64 __iomem *mtts;
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} tavor;
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struct {
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struct mthca_mpt_entry *mpt;
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__be64 *mtts;
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dma_addr_t dma_handle;
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} arbel;
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} mem;
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};
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struct mthca_pd {
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struct ib_pd ibpd;
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u32 pd_num;
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atomic_t sqp_count;
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struct mthca_mr ntmr;
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int privileged;
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};
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struct mthca_eq {
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struct mthca_dev *dev;
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int eqn;
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u32 eqn_mask;
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u32 cons_index;
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u16 msi_x_vector;
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u16 msi_x_entry;
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int have_irq;
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int nent;
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struct mthca_buf_list *page_list;
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struct mthca_mr mr;
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char irq_name[IB_DEVICE_NAME_MAX];
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};
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struct mthca_av;
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enum mthca_ah_type {
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MTHCA_AH_ON_HCA,
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MTHCA_AH_PCI_POOL,
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MTHCA_AH_KMALLOC
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};
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struct mthca_ah {
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struct ib_ah ibah;
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enum mthca_ah_type type;
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u32 key;
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struct mthca_av *av;
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dma_addr_t avdma;
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};
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/*
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* Quick description of our CQ/QP locking scheme:
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*
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* We have one global lock that protects dev->cq/qp_table. Each
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* struct mthca_cq/qp also has its own lock. An individual qp lock
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* may be taken inside of an individual cq lock. Both cqs attached to
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* a qp may be locked, with the cq with the lower cqn locked first.
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* No other nesting should be done.
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*
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* Each struct mthca_cq/qp also has an ref count, protected by the
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* corresponding table lock. The pointer from the cq/qp_table to the
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* struct counts as one reference. This reference also is good for
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* access through the consumer API, so modifying the CQ/QP etc doesn't
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* need to take another reference. Access to a QP because of a
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* completion being polled does not need a reference either.
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*
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* Finally, each struct mthca_cq/qp has a wait_queue_head_t for the
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* destroy function to sleep on.
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*
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* This means that access from the consumer API requires nothing but
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* taking the struct's lock.
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*
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* Access because of a completion event should go as follows:
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* - lock cq/qp_table and look up struct
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* - increment ref count in struct
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* - drop cq/qp_table lock
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* - lock struct, do your thing, and unlock struct
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* - decrement ref count; if zero, wake up waiters
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*
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* To destroy a CQ/QP, we can do the following:
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* - lock cq/qp_table
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* - remove pointer and decrement ref count
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* - unlock cq/qp_table lock
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* - wait_event until ref count is zero
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*
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* It is the consumer's responsibilty to make sure that no QP
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* operations (WQE posting or state modification) are pending when a
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* QP is destroyed. Also, the consumer must make sure that calls to
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* qp_modify are serialized. Similarly, the consumer is responsible
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* for ensuring that no CQ resize operations are pending when a CQ
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* is destroyed.
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*
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* Possible optimizations (wait for profile data to see if/where we
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* have locks bouncing between CPUs):
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* - split cq/qp table lock into n separate (cache-aligned) locks,
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* indexed (say) by the page in the table
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* - split QP struct lock into three (one for common info, one for the
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* send queue and one for the receive queue)
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*/
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struct mthca_cq_buf {
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union mthca_buf queue;
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struct mthca_mr mr;
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int is_direct;
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};
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struct mthca_cq_resize {
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struct mthca_cq_buf buf;
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int cqe;
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enum {
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CQ_RESIZE_ALLOC,
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CQ_RESIZE_READY,
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CQ_RESIZE_SWAPPED
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} state;
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};
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struct mthca_cq {
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struct ib_cq ibcq;
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spinlock_t lock;
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int refcount;
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int cqn;
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u32 cons_index;
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struct mthca_cq_buf buf;
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struct mthca_cq_resize *resize_buf;
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int is_kernel;
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/* Next fields are Arbel only */
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int set_ci_db_index;
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__be32 *set_ci_db;
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int arm_db_index;
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__be32 *arm_db;
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int arm_sn;
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wait_queue_head_t wait;
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struct mutex mutex;
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};
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struct mthca_srq {
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struct ib_srq ibsrq;
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spinlock_t lock;
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int refcount;
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int srqn;
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int max;
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int max_gs;
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int wqe_shift;
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int first_free;
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int last_free;
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u16 counter; /* Arbel only */
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int db_index; /* Arbel only */
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__be32 *db; /* Arbel only */
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void *last;
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int is_direct;
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u64 *wrid;
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union mthca_buf queue;
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struct mthca_mr mr;
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wait_queue_head_t wait;
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struct mutex mutex;
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};
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struct mthca_wq {
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spinlock_t lock;
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int max;
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unsigned next_ind;
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unsigned last_comp;
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unsigned head;
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unsigned tail;
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void *last;
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int max_gs;
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int wqe_shift;
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int db_index; /* Arbel only */
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__be32 *db;
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};
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struct mthca_qp {
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struct ib_qp ibqp;
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int refcount;
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u32 qpn;
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int is_direct;
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u8 port; /* for SQP and memfree use only */
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u8 alt_port; /* for memfree use only */
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u8 transport;
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u8 state;
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u8 atomic_rd_en;
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u8 resp_depth;
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struct mthca_mr mr;
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struct mthca_wq rq;
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struct mthca_wq sq;
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enum ib_sig_type sq_policy;
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int send_wqe_offset;
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int max_inline_data;
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u64 *wrid;
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union mthca_buf queue;
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wait_queue_head_t wait;
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struct mutex mutex;
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};
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struct mthca_sqp {
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struct mthca_qp qp;
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int pkey_index;
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u32 qkey;
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u32 send_psn;
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struct ib_ud_header ud_header;
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int header_buf_size;
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void *header_buf;
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dma_addr_t header_dma;
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};
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static inline struct mthca_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
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{
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return container_of(ibucontext, struct mthca_ucontext, ibucontext);
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}
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static inline struct mthca_fmr *to_mfmr(struct ib_fmr *ibmr)
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{
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return container_of(ibmr, struct mthca_fmr, ibmr);
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}
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static inline struct mthca_mr *to_mmr(struct ib_mr *ibmr)
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{
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return container_of(ibmr, struct mthca_mr, ibmr);
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}
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static inline struct mthca_pd *to_mpd(struct ib_pd *ibpd)
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{
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return container_of(ibpd, struct mthca_pd, ibpd);
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}
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static inline struct mthca_ah *to_mah(struct ib_ah *ibah)
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{
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return container_of(ibah, struct mthca_ah, ibah);
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}
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static inline struct mthca_cq *to_mcq(struct ib_cq *ibcq)
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{
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return container_of(ibcq, struct mthca_cq, ibcq);
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}
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static inline struct mthca_srq *to_msrq(struct ib_srq *ibsrq)
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{
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return container_of(ibsrq, struct mthca_srq, ibsrq);
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}
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static inline struct mthca_qp *to_mqp(struct ib_qp *ibqp)
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{
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return container_of(ibqp, struct mthca_qp, ibqp);
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}
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static inline struct mthca_sqp *to_msqp(struct mthca_qp *qp)
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{
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return container_of(qp, struct mthca_sqp, qp);
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}
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#endif /* MTHCA_PROVIDER_H */
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