mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 18:36:39 +07:00
6cd94d5e57
New and updated SoC support, notable changes include:
* bcm: brcmstb SMP support
* bcm: initial iproc/cygnus support
* exynos: Exynos4415 SoC support
* exynos: PMU and suspend support for Exynos5420
* exynos: PMU support for Exynos3250
* exynos: pm related maintenance
* imx: new LS1021A SoC support
* imx: vybrid 610 global timer support
* integrator: convert to using multiplatform configuration
* mediatek: earlyprintk support for mt8127/mt8135
* meson: meson8 soc and l2 cache controller support
* mvebu: Armada 38x CPU hotplug support
* mvebu: drop support for prerelease Armada 375 Z1 stepping
* mvebu: extended suspend support, now works on Armada 370/XP
* omap: hwmod related maintenance
* omap: prcm cleanup
* pxa: initial pxa27x DT handling
* rockchip: SMP support for rk3288
* rockchip: add cpu frequency scaling support
* shmobile: r8a7740 power domain support
* shmobile: various small restart, timer, pci apmu changes
* sunxi: Allwinner A80 (sun9i) earlyprintk support
* ux500: power domain support
Overall, a significant chunk of changes, coming mostly from
the usual suspects: omap, shmobile, samsung and mvebu, all of
which already contain a lot of platform specific code in
arch/arm.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt
cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn
hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE
hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp
m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1
W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW
5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8
sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz
+324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW
pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU
Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+
dF1lnQ7CXLQ=
=lFoH
-----END PGP SIGNATURE-----
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
163 lines
4.4 KiB
C
163 lines
4.4 KiB
C
/*
|
|
* Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
|
|
*/
|
|
|
|
/*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#ifndef __ASM_ARCH_MXC_COMMON_H__
|
|
#define __ASM_ARCH_MXC_COMMON_H__
|
|
|
|
#include <linux/reboot.h>
|
|
|
|
struct irq_data;
|
|
struct platform_device;
|
|
struct pt_regs;
|
|
struct clk;
|
|
struct device_node;
|
|
enum mxc_cpu_pwr_mode;
|
|
struct of_device_id;
|
|
|
|
void mx1_map_io(void);
|
|
void mx21_map_io(void);
|
|
void mx25_map_io(void);
|
|
void mx27_map_io(void);
|
|
void mx31_map_io(void);
|
|
void mx35_map_io(void);
|
|
void imx1_init_early(void);
|
|
void imx21_init_early(void);
|
|
void imx25_init_early(void);
|
|
void imx27_init_early(void);
|
|
void imx31_init_early(void);
|
|
void imx35_init_early(void);
|
|
void mxc_init_irq(void __iomem *);
|
|
void tzic_init_irq(void);
|
|
void mx1_init_irq(void);
|
|
void mx21_init_irq(void);
|
|
void mx25_init_irq(void);
|
|
void mx27_init_irq(void);
|
|
void mx31_init_irq(void);
|
|
void mx35_init_irq(void);
|
|
void imx1_soc_init(void);
|
|
void imx21_soc_init(void);
|
|
void imx25_soc_init(void);
|
|
void imx27_soc_init(void);
|
|
void imx31_soc_init(void);
|
|
void imx35_soc_init(void);
|
|
void epit_timer_init(void __iomem *base, int irq);
|
|
void mxc_timer_init(void __iomem *, int);
|
|
int mx1_clocks_init(unsigned long fref);
|
|
int mx21_clocks_init(unsigned long lref, unsigned long fref);
|
|
int mx25_clocks_init(void);
|
|
int mx27_clocks_init(unsigned long fref);
|
|
int mx31_clocks_init(unsigned long fref);
|
|
int mx35_clocks_init(void);
|
|
int mx31_clocks_init_dt(void);
|
|
struct platform_device *mxc_register_gpio(char *name, int id,
|
|
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
|
|
void mxc_set_cpu_type(unsigned int type);
|
|
void mxc_restart(enum reboot_mode, const char *);
|
|
void mxc_arch_reset_init(void __iomem *);
|
|
int mx51_revision(void);
|
|
int mx53_revision(void);
|
|
void imx_set_aips(void __iomem *);
|
|
void imx_aips_allow_unprivileged_access(const char *compat);
|
|
int mxc_device_init(void);
|
|
void imx_set_soc_revision(unsigned int rev);
|
|
unsigned int imx_get_soc_revision(void);
|
|
void imx_init_revision_from_anatop(void);
|
|
struct device *imx_soc_device_init(void);
|
|
|
|
enum mxc_cpu_pwr_mode {
|
|
WAIT_CLOCKED, /* wfi only */
|
|
WAIT_UNCLOCKED, /* WAIT */
|
|
WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
|
|
STOP_POWER_ON, /* just STOP */
|
|
STOP_POWER_OFF, /* STOP + SRPG */
|
|
};
|
|
|
|
enum mx3_cpu_pwr_mode {
|
|
MX3_RUN,
|
|
MX3_WAIT,
|
|
MX3_DOZE,
|
|
MX3_SLEEP,
|
|
};
|
|
|
|
void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
|
|
void imx_print_silicon_rev(const char *cpu, int srev);
|
|
|
|
void imx_enable_cpu(int cpu, bool enable);
|
|
void imx_set_cpu_jump(int cpu, void *jump_addr);
|
|
u32 imx_get_cpu_arg(int cpu);
|
|
void imx_set_cpu_arg(int cpu, u32 arg);
|
|
#ifdef CONFIG_SMP
|
|
void v7_secondary_startup(void);
|
|
void imx_scu_map_io(void);
|
|
void imx_smp_prepare(void);
|
|
#else
|
|
static inline void imx_scu_map_io(void) {}
|
|
static inline void imx_smp_prepare(void) {}
|
|
#endif
|
|
void imx_src_init(void);
|
|
void imx_gpc_init(void);
|
|
void imx_gpc_pre_suspend(bool arm_power_off);
|
|
void imx_gpc_post_resume(void);
|
|
void imx_gpc_mask_all(void);
|
|
void imx_gpc_restore_all(void);
|
|
void imx_gpc_hwirq_mask(unsigned int hwirq);
|
|
void imx_gpc_hwirq_unmask(unsigned int hwirq);
|
|
void imx_anatop_init(void);
|
|
void imx_anatop_pre_suspend(void);
|
|
void imx_anatop_post_resume(void);
|
|
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
|
|
void imx6q_set_int_mem_clk_lpm(bool enable);
|
|
void imx6sl_set_wait_clk(bool enter);
|
|
int imx_mmdc_get_ddr_type(void);
|
|
|
|
void imx_cpu_die(unsigned int cpu);
|
|
int imx_cpu_kill(unsigned int cpu);
|
|
|
|
#ifdef CONFIG_SUSPEND
|
|
void v7_cpu_resume(void);
|
|
void imx6_suspend(void __iomem *ocram_vbase);
|
|
#else
|
|
static inline void v7_cpu_resume(void) {}
|
|
static inline void imx6_suspend(void __iomem *ocram_vbase) {}
|
|
#endif
|
|
|
|
void imx6q_pm_init(void);
|
|
void imx6dl_pm_init(void);
|
|
void imx6sl_pm_init(void);
|
|
void imx6sx_pm_init(void);
|
|
void imx6q_pm_set_ccm_base(void __iomem *base);
|
|
|
|
#ifdef CONFIG_PM
|
|
void imx51_pm_init(void);
|
|
void imx53_pm_init(void);
|
|
void imx5_pm_set_ccm_base(void __iomem *base);
|
|
#else
|
|
static inline void imx51_pm_init(void) {}
|
|
static inline void imx53_pm_init(void) {}
|
|
static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
|
|
#endif
|
|
|
|
#ifdef CONFIG_NEON
|
|
int mx51_neon_fixup(void);
|
|
#else
|
|
static inline int mx51_neon_fixup(void) { return 0; }
|
|
#endif
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
void imx_init_l2cache(void);
|
|
#else
|
|
static inline void imx_init_l2cache(void) {}
|
|
#endif
|
|
|
|
extern struct smp_operations imx_smp_ops;
|
|
extern struct smp_operations ls1021a_smp_ops;
|
|
|
|
#endif
|