mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 18:46:39 +07:00
bc4abc3e5f
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
168 lines
4.2 KiB
C
168 lines
4.2 KiB
C
/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "common.h"
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#include "hardware.h"
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#define REG_SET 0x4
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#define REG_CLR 0x8
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#define ANADIG_REG_2P5 0x130
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#define ANADIG_REG_CORE 0x140
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#define ANADIG_ANA_MISC0 0x150
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#define ANADIG_USB1_CHRG_DETECT 0x1b0
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#define ANADIG_USB2_CHRG_DETECT 0x210
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#define ANADIG_DIGPROG 0x260
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#define ANADIG_DIGPROG_IMX6SL 0x280
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#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
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#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
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#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
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#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
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/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
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#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
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#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
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#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
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static struct regmap *anatop;
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static void imx_anatop_enable_weak2p5(bool enable)
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{
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u32 reg, val;
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regmap_read(anatop, ANADIG_ANA_MISC0, &val);
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/* can only be enabled when stop_mode_config is clear. */
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reg = ANADIG_REG_2P5;
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reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
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REG_SET : REG_CLR;
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regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
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}
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static void imx_anatop_enable_fet_odrive(bool enable)
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{
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regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
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BM_ANADIG_REG_CORE_FET_ODRIVE);
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}
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static inline void imx_anatop_enable_2p5_pulldown(bool enable)
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{
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regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
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BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
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}
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static inline void imx_anatop_disconnect_high_snvs(bool enable)
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{
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regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
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BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
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}
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void imx_anatop_pre_suspend(void)
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{
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if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
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imx_anatop_enable_2p5_pulldown(true);
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else
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imx_anatop_enable_weak2p5(true);
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imx_anatop_enable_fet_odrive(true);
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if (cpu_is_imx6sl())
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imx_anatop_disconnect_high_snvs(true);
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}
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void imx_anatop_post_resume(void)
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{
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if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
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imx_anatop_enable_2p5_pulldown(false);
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else
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imx_anatop_enable_weak2p5(false);
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imx_anatop_enable_fet_odrive(false);
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if (cpu_is_imx6sl())
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imx_anatop_disconnect_high_snvs(false);
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}
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static void imx_anatop_usb_chrg_detect_disable(void)
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{
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regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
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BM_ANADIG_USB_CHRG_DETECT_EN_B
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| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
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regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
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BM_ANADIG_USB_CHRG_DETECT_EN_B |
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BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
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}
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void __init imx_init_revision_from_anatop(void)
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{
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struct device_node *np;
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void __iomem *anatop_base;
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unsigned int revision;
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u32 digprog;
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u16 offset = ANADIG_DIGPROG;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
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anatop_base = of_iomap(np, 0);
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WARN_ON(!anatop_base);
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if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
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offset = ANADIG_DIGPROG_IMX6SL;
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digprog = readl_relaxed(anatop_base + offset);
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iounmap(anatop_base);
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switch (digprog & 0xff) {
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case 0:
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revision = IMX_CHIP_REVISION_1_0;
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break;
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case 1:
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revision = IMX_CHIP_REVISION_1_1;
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break;
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case 2:
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revision = IMX_CHIP_REVISION_1_2;
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break;
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case 3:
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revision = IMX_CHIP_REVISION_1_3;
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break;
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case 4:
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revision = IMX_CHIP_REVISION_1_4;
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break;
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case 5:
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/*
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* i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
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* as 'D' in Part Number last character.
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*/
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revision = IMX_CHIP_REVISION_1_5;
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break;
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default:
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revision = IMX_CHIP_REVISION_UNKNOWN;
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}
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mxc_set_cpu_type(digprog >> 16 & 0xff);
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imx_set_soc_revision(revision);
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}
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void __init imx_anatop_init(void)
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{
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anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
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if (IS_ERR(anatop)) {
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pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
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return;
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}
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imx_anatop_usb_chrg_detect_disable();
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}
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