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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2eaa03b5be
Replace sysdev classes and struct sys_device objects used for "core" power management by the PXA platform code with struct syscore_ops objects that are simpler. This reduces the code size and the kernel memory footprint. It also is necessary for removing sysdevs entirely from the kernel in the future. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
209 lines
4.5 KiB
C
209 lines
4.5 KiB
C
/*
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* linux/arch/arm/mach-pxa/clock-pxa3xx.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <mach/smemc.h>
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#include <mach/pxa3xx-regs.h>
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/* Ring Oscillator Clock: 60MHz */
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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#define ACCR_PCCE (1 << 11)
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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unsigned long acsr, xclkcfg;
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unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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acsr = ACSR;
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xl = acsr & 0x1f;
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xn = (acsr >> 8) & 0x7;
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hss = (acsr >> 14) & 0x3;
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XL = xl * BASE_CLK;
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XN = xn * XL;
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ro = acsr & ACCR_D0CS;
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
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HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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if (info) {
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pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
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RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
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(ro) ? "" : "in");
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pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
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XL / 1000000, (XL % 1000000) / 10000, xl);
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pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
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XN / 1000000, (XN % 1000000) / 10000, xn,
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(t) ? "" : "in");
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pr_info("HSIO bus clock: %d.%02dMHz\n",
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HSS / 1000000, (HSS % 1000000) / 10000);
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}
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return CLK / 1000;
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}
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/*
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* Return the current AC97 clock frequency.
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*/
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static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
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{
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unsigned long rate = 312000000;
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unsigned long ac97_div;
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ac97_div = AC97_DIV;
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/* This may loose precision for some rates but won't for the
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* standard 24.576MHz.
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*/
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rate /= (ac97_div >> 12) & 0x7fff;
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rate *= (ac97_div & 0xfff);
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return rate;
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}
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/*
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* Return the current HSIO bus clock frequency
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*/
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static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
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{
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unsigned long acsr;
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unsigned int hss, hsio_clk;
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acsr = ACSR;
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hss = (acsr >> 14) & 0x3;
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hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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return hsio_clk;
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}
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
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static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
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{
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unsigned long acsr = ACSR;
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unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
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return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
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df_clkdiv[(memclkcfg >> 16) & 0x3];
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}
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void clk_pxa3xx_cken_enable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA |= mask;
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else
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CKENB |= mask;
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}
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void clk_pxa3xx_cken_disable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA &= ~mask;
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else
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CKENB &= ~mask;
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}
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const struct clkops clk_pxa3xx_cken_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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};
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const struct clkops clk_pxa3xx_hsio_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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const struct clkops clk_pxa3xx_ac97_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_ac97_getrate,
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};
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const struct clkops clk_pxa3xx_smemc_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_smemc_getrate,
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};
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static void clk_pout_enable(struct clk *clk)
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{
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OSCC |= OSCC_PEN;
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}
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static void clk_pout_disable(struct clk *clk)
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{
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OSCC &= ~OSCC_PEN;
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}
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const struct clkops clk_pxa3xx_pout_ops = {
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.enable = clk_pout_enable,
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.disable = clk_pout_disable,
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};
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#ifdef CONFIG_PM
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static uint32_t cken[2];
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static uint32_t accr;
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static int pxa3xx_clock_suspend(void)
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{
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cken[0] = CKENA;
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cken[1] = CKENB;
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accr = ACCR;
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return 0;
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}
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static void pxa3xx_clock_resume(void)
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{
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ACCR = accr;
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CKENA = cken[0];
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CKENB = cken[1];
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}
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#else
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#define pxa3xx_clock_suspend NULL
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#define pxa3xx_clock_resume NULL
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#endif
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struct syscore_ops pxa3xx_clock_syscore_ops = {
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.suspend = pxa3xx_clock_suspend,
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.resume = pxa3xx_clock_resume,
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};
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