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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9ab4650f71
Instead of reading the silicon version from ROM, we should read the SREV register from the IIM. Freescale has dropped all support for MX51 REV1.0, only MX51 REV 2.0 and 3.0 are valid. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
140 lines
3.0 KiB
C
140 lines
3.0 KiB
C
/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* This file contains the CPU initialization code.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <mach/hardware.h>
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#include <asm/io.h>
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static int cpu_silicon_rev = -1;
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#define IIM_SREV 0x24
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static int get_mx51_srev(void)
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{
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void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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if (rev == 0x0)
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return IMX_CHIP_REVISION_2_0;
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else if (rev == 0x10)
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return IMX_CHIP_REVISION_3_0;
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return 0;
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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* -EINVAL - not a mx51
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*/
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int mx51_revision(void)
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{
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if (!cpu_is_mx51())
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return -EINVAL;
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if (cpu_silicon_rev == -1)
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cpu_silicon_rev = get_mx51_srev();
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return cpu_silicon_rev;
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}
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EXPORT_SYMBOL(mx51_revision);
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#ifdef CONFIG_NEON
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/*
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* All versions of the silicon before Rev. 3 have broken NEON implementations.
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* Dependent on link order - so the assumption is that vfp_init is called
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* before us.
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*/
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static int __init mx51_neon_fixup(void)
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{
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if (!cpu_is_mx51())
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return 0;
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if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
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elf_hwcap &= ~HWCAP_NEON;
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pr_info("Turning off NEON support, detected broken NEON implementation\n");
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}
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return 0;
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}
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late_initcall(mx51_neon_fixup);
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#endif
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static int get_mx53_srev(void)
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{
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void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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if (rev == 0x0)
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return IMX_CHIP_REVISION_1_0;
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else if (rev == 0x10)
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return IMX_CHIP_REVISION_2_0;
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return 0;
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}
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/*
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* Returns:
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* the silicon revision of the cpu
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* -EINVAL - not a mx53
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*/
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int mx53_revision(void)
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{
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if (!cpu_is_mx53())
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return -EINVAL;
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if (cpu_silicon_rev == -1)
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cpu_silicon_rev = get_mx53_srev();
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return cpu_silicon_rev;
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}
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EXPORT_SYMBOL(mx53_revision);
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static int __init post_cpu_init(void)
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{
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unsigned int reg;
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void __iomem *base;
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if (cpu_is_mx51() || cpu_is_mx53()) {
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if (cpu_is_mx51())
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base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
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else
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base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
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__raw_writel(0x0, base + 0x40);
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__raw_writel(0x0, base + 0x44);
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__raw_writel(0x0, base + 0x48);
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__raw_writel(0x0, base + 0x4C);
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reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
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__raw_writel(reg, base + 0x50);
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if (cpu_is_mx51())
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base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
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else
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base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
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__raw_writel(0x0, base + 0x40);
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__raw_writel(0x0, base + 0x44);
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__raw_writel(0x0, base + 0x48);
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__raw_writel(0x0, base + 0x4C);
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reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
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__raw_writel(reg, base + 0x50);
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}
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return 0;
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}
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postcore_initcall(post_cpu_init);
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